Designing larger than ever SoC, integrating multiple ARM’s Cortex-A15 and Cortex-A9 microprocessor cores as well as complexes IP functions like HDMI controller, DDR3 Memory controller, Ethernet, SATA or PCI Express controller are pushing designers to search for better price, performance and area tradeoffs and the SoC interconnect plays a vital role in serving this need. Using an advanced Network-on-Chip (NoC) like Arteris FlexNoC is an efficient solution to optimize the SoC and get the best possible return on the high investment linked with state of the art SoC development, by launching the IC in the right market window and benefit from a TTM advantage over the competition. Architects also want to virtually prototype their design, as it can be a good way to run these price, performance and area tradeoffs at early stages of the design, that they can do using Carbon’s SoCDesigner Plus, and prove their design assumptions before committing to the design implementation.
The joint Carbon/Arteris solution offers design teams a way to easily create and import accurate Arteris FlexNoC interconnect models for Carbon SoCDesigner Plus: the new Carbon/Arteris flow allows Carbon’s SoCDesigner Plus users to use Arteris FlexNoC to configure their NoC interconnect fabric IP and then upload the configuration to Carbon IP Exchange. The web portal then creates a 100% accurate virtual model of the configuration and makes it available for download and use in SoCDesigner Plus. “We see strong demand for models of Arteris’ NoC interconnect IP,” states Bill Neifert, chief technology officer at Carbon Design Systems®, the leading supplier of virtual platform and secure model solutions. “Our partnership with Arteris enables engineers to make architectural decisions and design tradeoffs based upon a 100%-accurate virtual representation.”
“Simulation with virtual models of our NoC interconnect IP are the best way to make system-on-chip architectural optimizations and tradeoffs,” comments Kurt Shuler, Arteris’ vice president of marketing. “By partnering with Carbon to make 100% accurate models of our IP available on Carbon IP Exchange, we are empowering design teams to utilize virtual models earlier in the design process.”
Going on Carbon IP Exchange web portal, we can see that the partnership allow to run a secured flow: the FlexNoC model is compiled directly from Arteris’s register transfer level (RTL) code and maintains 100% functional accuracy. The model integrates directly with Carbon’s SoC Designer Plus virtual platform. There is no “interpretation”, no modeling task in between the RTL source code from Arteris and the virtual prototyping usage within Carbon SoCDesigner Plus.
To learn more about FlexNoC IP from Arteris availability in IP Exchange web portal from Carbon design Systems, just go here.
By Eric Esteve from IPNESTShare this post via: