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TSMC Financial Status Plus OIP Update!

TSMC Financial Status Plus OIP Update!
by Daniel Nenni on 07-05-2011 at 8:00 am

Interesting notes from my most recent Taiwan trip: Taiwan unemployment is at a record low. Scooters once again fill the streets of Hsinchu! TSMC will be passing out record bonuses to a record amount of people. TSMC Fab expansions are ahead of schedule. The new Fab 15 in Taichung went up amazingly fast with equipment moving in later… Read More


TSMC Versus Intel: The Race to Semiconductors in 3D!

TSMC Versus Intel: The Race to Semiconductors in 3D!
by Daniel Nenni on 06-26-2011 at 4:00 pm

While Intel is doing victory laps in the race to a 3D transistor (FinFet) @ 22nm, TSMC is in production with 3D IC technology. A 3D IC is a chip in which two or more layers of active electronic components are integrated both vertically and horizontally into a single circuit. The question is which 3D race is more important to the semiconductor… Read More


New TSMC 28nm Design Ecosystem!

New TSMC 28nm Design Ecosystem!
by Daniel Nenni on 05-28-2011 at 9:23 pm

TSMC rolled out the new reference flows for 28nm design as part of the Open Innovation Platform. The biggest surprise (to me) is that Cadence is STILL in the TSMC reference flows!

The updated TSMC OIP wiki is here, the Reference Flow 12.0 wiki can be found here, the AMS 2.0 reference flow wiki is here, and the official TSMC PR is here. Read More


TSMC Conference Call is a 6.5 on the Richter Scale

TSMC Conference Call is a 6.5 on the Richter Scale
by Daniel Nenni on 04-28-2011 at 12:17 am

TSMC continues to drive the economic recovery with impressive Q1 numbers and an even more impressive Q2 and Q3 outlook. TSMC is my economic bellwether due to its diverse customer base and shear volume of consumer electronics silicon. The big surprise in the 1 hour Q1 conference call is a new Giga Fab (#15) ground breaking this year… Read More


Process Design Kits: PDKs, iPDKs, openPDKs

Process Design Kits: PDKs, iPDKs, openPDKs
by Paul McLellan on 03-24-2011 at 5:28 pm

One of the first things that needs to be created when bringing up a new process is the Process Design Kit, or PDK. Years ago, back when I was running the custom IC business line at Cadence, we had a dominant position with the Virtuoso layout editor and so creating a PDK really meant creating a Virtuoso PDK, and it was a fairly straightforward… Read More


Moore’s Law and Semiconductor Design and Manufacturing

Moore’s Law and Semiconductor Design and Manufacturing
by Daniel Nenni on 03-12-2011 at 4:51 am

The semiconductor design and manufacturing challenges at 40nm and 28nm are a direct result ofMoore’s Law, the climbing transistor count and shrinking geometries. It’s a process AND design issue and the interaction is at the transistor level. Transistors may be shrinking, but atoms aren’t. So now it actually matters when even… Read More


TSMC 2011 Technology Symposium Theme Explained

TSMC 2011 Technology Symposium Theme Explained
by Daniel Nenni on 03-09-2011 at 6:49 pm

The 17[SUP]th[/SUP] Annual TSMC Technology Symposium will be held in San Jose California on April 5[SUP]th[/SUP], 2011. Dr. Morris Chang will again be the keynote speaker. The theme this year is “Trusted Technology and Capacity Provider”and I think it’s important to not only hear what people are saying but also understand why… Read More


Semiconductor Power Crisis and TSMC!

Semiconductor Power Crisis and TSMC!
by Daniel Nenni on 03-02-2011 at 8:48 pm

Power grids all over the world are already overloaded even without the slew of new electronic gadgets and cars coming out this year. At ISSCC, Dr. Jack Sun, TSMC Vice President of R&D and Chief Technology Officer made the comparison of a human brain to the closest thing available in silicon, a graphical processing unit (GPU).… Read More


Custom and AMS Design

Custom and AMS Design
by Daniel Payne on 02-21-2011 at 10:06 pm

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For IC designers creating full-custom or AMS designs there are plenty of challenges to getting designs done right on the first spin of silicon. Let me give you a sneak peek into what’s being discussed at the EDA Tech Forum in Santa Clara, CA on March 10th that will be of special interest to you:

3D TSV (Through Silicon Vias) are… Read More


TSMC Raises The Semiconductor Bar With 450mm!

TSMC Raises The Semiconductor Bar With 450mm!
by Daniel Nenni on 02-03-2011 at 2:34 pm

During the most recent conference call (transcript), TSMC not only beat revised estimates and announced record spending levels for 2011, Morris Chang also officially announced that a 450mm fab (Fab 12 Phase VI) is currently in the planning stages with target production @ 20nm in 2015. This is HUGE!

According to Morris Chang:

“ForRead More