As I mentioned in my previous post, the TSMC investor call this month was very interesting and Morris Chang was in fine form during the Q&A. As a semiconductor professional I think some of the questions are ridiculous but maybe they have value to the financial people. This one question from Randy, who I think is very astute, is … Read More
Fan-Out Wafer Level Processing Gets Boost from Mentor TSMC Collaboration
I caught up with John Ferguson of Mentor Graphics this week to learn more about a recent announcement that TSMC has extended its collaboration with Mentor in the area of Fan-Out Wafer Level Processing (FOWLP).
In March of last year Mentor and TSMC announced that they were collaborating on a design and verification flow for TSMC’s… Read More
IP development strategy and hockey
One of the greatest hockey players of all time, Wayne Gretzky, provided a quote that has also been applied to the business world — “I skate to where the puck will be, not to where it has been.” It strikes me that this philosophy directly applies to IP development, as well. Engineering firms providing IP must anticipate… Read More
Three Interesting Things from TSMC!
First, the TSMC Museum of Innovation is now open and it’s quite impressive. Located right below Fab 12, it is definitely worth an hour of your time. Second, Morris Chang was on the investor call which made it much more interesting, especially his comments on the recent Report to the President on U.S. semiconductor leadership. Third,… Read More
Making the Move from 28nm to FinFET!
If you click FinFET in the SemiWiki.com Latest News: navigation bar at the top of this page you will get a list of 86 blogs that have been viewed more than 600,000 times. If you go to the last blogs on the list, meaning the first blogs to be published, you will see a three part series, “Introduction to FinFET Technology” written by Tom Dillinger… Read More
Analog Bits and TSMC!
As a long time semiconductor IP professional I can tell you for a fact that it is one of the most challenging segments of semiconductor design. Given the growing criticality of semiconductor IP, the challenges of being a leading edge IP provider are increasing and may be at a breaking point. The question now is: What does it take to … Read More
The 2017 Leading Edge Semiconductor Landscape
In early September of 2016 I published an article “The 2016 Leading Edge Semiconductor Landscape” that proved to be very popular with many views, comments and reposting’s. Since I wrote that article a lot of new data has become available enabling some projections to be replaced by actual values and new analysis… Read More
IEDM 2016 – 7nm Shootout
In the first session of IEDM on Monday, December 5th there were two papers presented on 7nm processes. The first paper was from TSMC and the second paper was from the Global Alliance of GLOBALFOUNDRIES, IBM and Samsung.… Read More
Advanced Semiconductor Process Cost Trends
The cost trend for leading edge semiconductor technologies is a subject of some controversy in the industry. Cost is a complex issue with many interacting factors and much of the information out in the industry is in my opinion misleading or incorrect. In this article, I will discuss each of the factors as well as present a view of … Read More
Design for Fanout Packaging
In constant pursuit of improved performance, power and cost, chip and system designers always want to integrate more functions together because this minimizes inter-device loads (affecting performance and power) and bill of materials on the board (affecting cost). However it generally isn’t possible to integrate … Read More