The 5nm foundry node saw the arrival of 6-track standard cells with four narrow routing tracks between wide power/ground rails (Figure 1a), with minimum pitches of around 30 nm [1]. The routing tracks require cuts [2] with widths comparable to the minimum half-pitch, to enable the via connections to the next metal layer with the… Read More
The EUV Divide and Intel Foundry Services
The EUV Divide
I was recently updating an analysis I did last year that looked at EUV system supply and demand, while doing this I started thinking about Intel and their Fab portfolio.
If you look at Intel’s history as a microprocessor manufacturer, they are typically ramping up their newest process node (n), in volume production… Read More
Horizontal, Vertical, and Slanted Line Shadowing Across Slit in Low-NA and High-NA EUV Lithography Systems
EUV lithography systems continue to be the source of much hope for continuing the pace of increasing device density on wafers per Moore’s Law. Recently, although EUV systems were originally supposed to help the industry avoid much multipatterning, it has not turned out to be the case [1,2]. The main surprise has been the
Pattern Shifts Induced by Dipole-Illuminated EUV Masks
As EUV lithography is being targeted towards pitches of 30 nm or less, fundamental differences from conventional DUV lithography become more and more obvious. A big difference is in the mask use. Unlike other photolithography masks, EUV masks are absorber patterns on a reflective multilayer rather than a transparent substrate.… Read More
Revisiting EUV Lithography: Post-Blur Stochastic Distributions
In previous articles, I had looked at EUV stochastic behavior [1-2], primarily in terms of the low photon density resulting in shot noise, described by the Poisson distribution [3]. The role of blur to help combat the randomness of EUV photon absorption and secondary electron generation and migration was also recently considered… Read More
Losing Lithography: How the US Invented, then lost, a Critical Chipmaking Process
Lithography is arguably the most important step in semiconductor manufacturing. Today’s state-of-the-art EUV scanners are incredibly complex machines that cost as much as a new Boeing jetliner.
From humble beginnings in 1984 as a joint venture with Philips, ASML has grown to become the world’s second largest chip equipment… Read More
The Challenge of Working with EUV Doses
Recently, a patent application from TSMC [1] revealed target EUV doses used in the range of 30-45 mJ/cm2. However, it was also acknowledged in the same application that such doses were too low to prevent defects and roughness. Recent studies [2,3] have shown that by considering photon density along with blur, the associated shot… Read More
Blur, not Wavelength, Determines Resolution at Advanced Nodes
Lithography has been the driving force for shrinking feature sizes for decades, and the most easily identified factor behind this trend is the reduction of wavelength. G-line (436 nm wavelength) was used for 0.5 um in the late 1980s [1], and I-line (365 nm wavelength) was used down to 0.3 um in the 1990s [2]. Then began the era of deep-ultraviolet… Read More
Cautions In Using High-NA EUV
High-NA EUV has received a lot of attention ever since Intel put the spotlight on its receiving the first 0.55 NA EUV tool from ASML [1], expected in 2025. EUV itself has numerous issues which have been enumerated by myself and others, most notoriously the stochastic defects issue. There are also a host of issues related to the propagation… Read More
Stochastic Effects from Photon Distribution Entropy in High-k1 EUV Lithography
Recent advances in EUV lithography have largely focused on “low-k1” imaging, i.e., features with pitches less than the wavelength divided by the numerical aperture (k1<0.5). With a nominal wavelength of 13.5 nm and a numerical aperture of 0.33, this means sub-40 nm pitches. It is naturally expected that larger… Read More
Unlocking the cloud: A new era for post-tapeout flow for semiconductor manufacturing