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FPGA
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How to make ESL really work – see EDPS

How to make ESL really work – see EDPS
by John Swan on 04-12-2013 at 6:53 pm
Categories: FPGA, Xilinx

The Electronic Design Process Symposium (EDPS) is April 18 & 19 in Monterey. The workshop style Symposium is in its 20[SUP]th[/SUP] year. The first session is titled “ESL & Platforms”, which immediately follows the opening Keynote address by Ivo Bolsens, CTO of Xilinx.

In his keynote presentation Ivo will present how… Read More

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High Level Synthesis – It’s for Real

High Level Synthesis – It’s for Real
by Luke Miller on 04-11-2013 at 8:30 pm
Categories: FPGA, Xilinx

It was spring 2010 and I was asked to attend an HLS (High Level Synthesis) meeting. To be honest I cringed, after my bad relationship with Accel DSP and broken promises my heart was all walled up and needed counseling. But my management had a way of making me an offer I could not refuse, like keeping my job. So reluctantly I went. Does your… Read More

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A Non Deterministic Timing Problem

A Non Deterministic Timing Problem
by Luke Miller on 04-07-2013 at 2:00 pm
Categories: FPGA, Xilinx

When I was not messing around with FPGA Research and Development, or Algorithms, I was often called into the lab or field and presented this type of scenario… Most of the time, the fix was the same…

At least a few times a year, I’d get the call. Sometimes a panic in the voice, or sometimes defeat. And who wouldn’t be defeated? After… Read More

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TSMC to Talk About 10nm at Symposium Next Week

TSMC to Talk About 10nm at Symposium Next Week
by Daniel Nenni on 04-02-2013 at 8:05 pm
Categories: EDA, Foundries, FPGA, TSMC

Given the compressed time between 20nm and 16nm, twelve months versus the industry average twenty four months, it is time to start talking about 10nm, absolutely. Next Tuesday is the 19th annual TSMC Technology Symposium keynoted of course by the Chairman, Dr. Morris Chang.

Join the 2013 TSMC Technology Symposium. Get the latest… Read More

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RTDA at Altera

RTDA at Altera
by Paul McLellan on 03-12-2013 at 8:05 pm
Categories: EDA, FPGA

I talked to Yaron Kretchmer of Altera to find out how they are using RTDA’s products. I believe that Altera are the oldest customer of RTDA, dating back over 15 years, originally used by the operations team around the test floor before propagating out in the EDA and software worlds more recently.

Altera use two RTDA tools, LicenceMonitor… Read More

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Intel and Altera Sign on for 14nm

Intel and Altera Sign on for 14nm
by Ed McKernan on 02-25-2013 at 5:00 pm
Categories: Foundries, FPGA, Intel Foundry

The announcement today that Intel will be a Foundry for Altera at 14nm is a significant turning point for the Semiconductor Industry and Intel’s Foundry fortunes of which the full ramifications are not likely to be understood by analysts. As a long time follower of Intel and a former co-founder of an FPGA startup (Cswitch), it has… Read More

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Help, my IP has fallen and can’t get up

Help, my IP has fallen and can’t get up
by Don Dingee on 02-03-2013 at 8:10 pm
Categories: EDA, FPGA, IP, Synopsys

We’ve been talking about the different technologies for FPGA-based SoC prototyping a lot here in SemiWiki. On the surface, the recent stories all start off pretty much the same: big box, Xilinx Virtex-7, wanna go fast and see more of what’s going on in the design. This is not another one of those stories. I recently sat down with Mick… Read More

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Zynq out of the box, in FPGA-based prototyping

Zynq out of the box, in FPGA-based prototyping
by Don Dingee on 12-10-2012 at 11:24 am
Categories: Aldec, EDA, FPGA

Roaming around the hall at ARM TechCon 2012 left me with eight things of note, but one of the larger ideas showing up everywhere is the Xilinx Zynq. Designers are enthralled with the idea of a dual-core ARM Cortex-A9 closely coupled with programmable logic.… Read More

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3D Architectures for Semiconductor Integration and Packaging

3D Architectures for Semiconductor Integration and Packaging
by Paul McLellan on 12-10-2012 at 4:00 am
Categories: FPGA, Xilinx

There is obviously a lot going on in 3D IC these days. And I don’t mean at the micro level of FinFETs which is also a way of going vertical. I mean through-silicon-via (TSV) based approaches for either stacking die or putting them on an interposer. Increasingly the question is no longer if this technology will be viable (there… Read More

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An FPGA Design Flow with Aldec Tools

An FPGA Design Flow with Aldec Tools
by Daniel Payne on 12-04-2012 at 12:19 pm
Categories: Aldec, EDA, FPGA

I’ve used FPGA vendor-supplied tools from both Xilinxand Lattice Semibefore, so I wanted to see what EDA tools Aldec has to offer for FPGA design. I read the Aldecwhite paper, Corporate Standardization of FPGA Design Flow, and summarize what I found.… Read More