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Webinar: ASICs Unlock Deep Learning Innovation

Webinar: ASICs Unlock Deep Learning Innovation
by Daniel Nenni on 04-27-2018 at 12:00 pm

In March, an AI event was held at the Computer History Museum entitled “ASICs Unlock Deep Learning Innovation.” Along with Samsung, Amkor Technology and Northwest Logic, eSilicon explored how these companies form an ecosystem to develop deep learning chips for the next generation of AI applications. There was also a keynote … Read More


EDA CEO Outlook 2018 Partly Cloudy

EDA CEO Outlook 2018 Partly Cloudy
by Daniel Nenni on 04-16-2018 at 7:00 am

The funniest line of the EDA CEO Outlook event was that we should rename our Amazon Echos Wally. Yes Wally is that smart and he remembers pretty much everything. I wish I could rename my Echo Wally because my daughter in-law is named Alexa so we have to turn it off when she is over. The discussion took an interesting turn with EDA in the … Read More


Intel Based FPGA Prototyping Webinar Replay

Intel Based FPGA Prototyping Webinar Replay
by Daniel Nenni on 04-13-2018 at 7:00 am

Due to the overwhelming response, here is the first part of the webinar that I did with S2C and a link to the replay. Richard Chang, Vice President of Engineering at S2C did the technical part of the webinar. Richard has a Masters degree in Electrical engineering from the University at Buffalo and more than 20 years experience designing… Read More


Embracing Architectural Intent

Embracing Architectural Intent
by Alex Tan on 04-10-2018 at 12:00 pm

During DVCon 2018 in San Jose, one topic widely covered was the necessity of describing and capturing intent. Defining our design intent up-front is crucial to the overall success of a design implementation. It is not limited to applying a process level intent, such as the use of verification intent with embedded assertions in … Read More


EDA CEO Outlook 2018

EDA CEO Outlook 2018
by Daniel Nenni on 04-06-2018 at 12:00 pm

The EDA CEO outlook took an interesting turn last night but before I get into that I will offer a few comments about the start of the show. I attend this event every year for the content but also for the networking. It isn’t everyday you get to hang out with semiconductor industry elite and have candid conversations over food and drinks.… Read More


FlexE at SoC IP Days with Open Silicon

FlexE at SoC IP Days with Open Silicon
by Daniel Nenni on 03-30-2018 at 12:00 pm

On Thursday April 5th the Design and Reuse SoC IP days continues in Santa Clara at the Hyatt Regency (my favorite hangout). SemiWiki is a co-sponsor and I am Chairman of the IP Security Track. More than 400 people have registered thus far and I expect a big turnout, if you look at the program you will see why. You should also know that registration… Read More


Aart de Geus At the Heart of Impact!

Aart de Geus At the Heart of Impact!
by Alex Tan on 03-26-2018 at 7:00 am

At the Silicon Valley SNUG 2018, Synopsys Chairman and co-CEO Dr. Aart de Geuss gave his keynote speech addressing attendees on how far we have evolved, and at times encountered the aha factor that helps propel us to the next level. He explored trends as well as the current state of his company solution offerings.


Moore’s Law, Digital
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Free Webinar: Silvaco 3D Solver Based Extraction for Device and Circuit Designers

Free Webinar: Silvaco 3D Solver Based Extraction for Device and Circuit Designers
by admin on 03-20-2018 at 12:00 pm

Designers spend a lot of time looking at their layouts in 2D. This is done naturally because viewing in 2D is faster and simpler than in 3D. It helps that humans are good at extrapolating from 2D to 3D. Analysis software, such as extraction software also spend a lot of time looking at layouts in 2D. While this is fine for approximate results,… Read More


Don’t Stand Between The Anonymous Bug and Tape-Out (Part 2 of 2)

Don’t Stand Between The Anonymous Bug and Tape-Out (Part 2 of 2)
by Alex Tan on 03-16-2018 at 7:00 am


The second panel is about system coverage and big data. Coverage metrics have been used to gauge the quality of verification efforts during development. At system level, there are still no standardized metrics to measure full coverage. The emergence of PSS, better formal verification, enhanced emulation and prototyping techniques… Read More


Webinar Alert – Embedded Monitoring of Process and Voltage in SoCs

Webinar Alert – Embedded Monitoring of Process and Voltage in SoCs
by Daniel Payne on 03-13-2018 at 12:00 pm

In the old days to learn about new semiconductor IP you would have to schedule a sales call, listen to the pitch, then decide if the IP was promising or not. Today we have webinars which offer a lot less drama than a sales call, plus you get to ask your questions by typing away at the comfort of your desk, hopefully wearing headphones as … Read More