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Meeting Analog Reliability Challenges Across the Product Life Cycle

Meeting Analog Reliability Challenges Across the Product Life Cycle
by Daniel Payne on 08-14-2018 at 12:00 pm

Create a panel discussion about analog IC design and reliability and my curiosity is instantly piqued, so I attended a luncheon discussion at #55DAC moderated by Steven Lewis of Cadence. The panelists were quite deep in their specialized fields:… Read More


SEMICON West – Leading Edge Lithography and EUV

SEMICON West – Leading Edge Lithography and EUV
by Scotten Jones on 08-13-2018 at 7:00 am

At SEMICON West I attended the imec technology forum, multiple Tech Spot presentations and conducted a number of interviews relevant to advanced lithography and EUV. In this article I will summarize what I learned plus make some comments on the outlook for EUV.… Read More


Netspeed and NSITEXE talk about automotive design trends at 55DAC

Netspeed and NSITEXE talk about automotive design trends at 55DAC
by Tom Simon on 08-02-2018 at 12:00 pm

DAC is where both sides of the design equation come together for discussion and learning. This is what makes attending DAC discussion panels so interesting; you are going to hear from providers of tools, methodologies and IP as well as those who need to use them to deliver working solutions. There are few places where the interplay… Read More


Daniel’s #55DAC Trip Report

Daniel’s #55DAC Trip Report
by Daniel Payne on 07-29-2018 at 7:00 am

Another year, another DAC, and last month it was #55DAC in SFO and the first thing that I noticed was that the event was no longer located in the traditional North or South Halls, rather we were in the smaller, Moscone West on two floors, almost like a 3D FinFET. Checkin to get my badge was highly automated and oh so fast, well done.… Read More


1-on-1 with Anirudh Devgan, President, Cadence

1-on-1 with Anirudh Devgan, President, Cadence
by Tom Dillinger on 07-27-2018 at 12:00 pm

At the Design Automation Conference, no one is busier than an EDA company executive — conference panels, product launch briefings, customer meetings, and corporate dinners all place considerable demands on their time. I was fortunate enough to be able to meet with Anirudh Devgan, President of Cadence, at the recent DAC55 in San… Read More


Optimization and Reliability for FinFET designs at #55DAC

Optimization and Reliability for FinFET designs at #55DAC
by Daniel Payne on 07-25-2018 at 7:00 am

TSMC is the leading foundry worldwide and they make a big splash each year at the DAC exhibit and conference, so I stopped by their theatre area during the presentation from IP vendor Moortec to see what’s new this year. Stephen Crosher was the presenter from Moortec and we had exchanged emails before, so this was the first time… Read More


Automotive is setting the goalposts for next generation designs

Automotive is setting the goalposts for next generation designs
by Tom Simon on 07-24-2018 at 12:00 pm

Automotive applications are having a tremendous influence on semiconductor design. This influence is coming from innovations in cloud computing, artificial intelligence, communications, sensors that all serve the requirements of the automotive market. It should come as no surprise that ADAS and autonomous driving are … Read More


FDSOI Status and Roadmap

FDSOI Status and Roadmap
by Scotten Jones on 07-23-2018 at 7:00 am

FDSOI is gaining traction in the market place. At their foundry forum in May, Samsung announced they have 17 FDSOI products in high volume manufacturing (you can read Tom Dilliger’s write up of the Samsung Foundry Forum here). At SEMICON West in July, GLOBALFOUNDRIES (GF) announced FDSOI design wins worth $2 billion dollars in … Read More


SEMICON West – Soitec is becoming a key enabler

SEMICON West – Soitec is becoming a key enabler
by Scotten Jones on 07-22-2018 at 7:00 am

A variety of growing and emerging segments of the semiconductor industry rely on Silicon-On-Insulator (SOI) wafers. Soitec is the primary source for SOI wafers particularly on 300mm. On Tuesday at SEMICON I got to sit down with Bernard Aspar, Soitec’s Executive Vice President, Communication & Power BU and Christophe… Read More


Maximize Bandwidth in your Massively Parallel AI SoCs?

Maximize Bandwidth in your Massively Parallel AI SoCs?
by Daniel Nenni on 07-20-2018 at 12:00 pm

Artificial Intelligence is one of the most talked about topics on the conference circuit this year and I don’t expect that to change anytime soon. AI is also one of the trending topics on SemiWiki with organic search bringing us a wealth of new viewers. You may also have noticed that AI is a hot topic for webinars like the one I am writing… Read More