Ceva webinar AI Arch SEMI 800X100 250625
WP_Term Object
(
    [term_id] => 50
    [name] => Events
    [slug] => events
    [term_group] => 0
    [term_taxonomy_id] => 50
    [taxonomy] => category
    [description] => 
    [parent] => 0
    [count] => 1374
    [filter] => raw
    [cat_ID] => 50
    [category_count] => 1374
    [category_description] => 
    [cat_name] => Events
    [category_nicename] => events
    [category_parent] => 0
    [is_post] => 
)

VLSI Symposium 2020 – Imec Buried Power Rail

VLSI Symposium 2020 – Imec Buried Power Rail
by Scotten Jones on 07-26-2020 at 10:00 am

thl61591895083576 Page 04

The 2020 VLSI Technology Symposium was held as a virtual conference from June 14th through June 19th. At the symposium Imec gave an interesting paper on Buried Power Rails (BPR) and I had a chance to interview one of the authors, Anshul Gupta.

As logic devices continue to scale down metal pitch is reaching a limit. Imec defines a pitch… Read More


How yieldHUB Helps Bring a New Product to Market

How yieldHUB Helps Bring a New Product to Market
by Mike Gianfagna on 07-24-2020 at 10:00 am

Screen Shot 2020 07 14 at 4.01.42 PM

 

Collecting and analyzing semiconductor test data is a subject that holds a special place for me. Developing a factory data collection and analysis system was my first job out of school. The company was RCA, and the factories were in Findlay, Ohio (analog/mixed signal) and West Palm Beach, Florida (digital). There was a pilot… Read More


Thermo-compression bonding for Large Stacked HBM Die

Thermo-compression bonding for Large Stacked HBM Die
by Tom Dillinger on 07-24-2020 at 8:00 am

HMB stack

Summary

Thermo-compression bonding is used in heterogeneous 3D packaging technology – this attach method was applied to the assembly of large (12-stack and 16-stack) high bandwidth memory (HBM) die, with significant bandwidth and power improvements over traditional microbump attach.

Introduction

The rapid growth of heterogeneous… Read More


The Official SemiWiki Virtual DAC 2020 Must See List!

The Official SemiWiki Virtual DAC 2020 Must See List!
by Daniel Nenni on 07-17-2020 at 2:00 pm

57DAC Logo SemiWiki

This is going to be a record setting year for DAC content and attendance, absolutely!

My first DAC was in 1984 in Albuquerque New Mexico, right out of College, and I married my beautiful wife two months later. Thirty six DAC’s later I have four grown children, grandchildren, and the number one semiconductor design portal in the world.… Read More


A tour of Cliosoft’s participation at DAC 2020 with Simon Rance

A tour of Cliosoft’s participation at DAC 2020 with Simon Rance
by Mike Gianfagna on 07-15-2020 at 10:00 am

Simon Rance

As chip complexity grows, so does the need for a well-thought-out design data management strategy.  This is a hot area, and Cliosoft is in the middle of it.  When I was at eSilicon, we used Cliosoft technology to manage the design and layout of high-performance analog designs across widely separated design teams. The tool worked… Read More


SystemC Methodology for Virtual Prototype at DVCon USA

SystemC Methodology for Virtual Prototype at DVCon USA
by Daniel Payne on 07-13-2020 at 10:00 am

Register Model min

DVCon was the first EDA conference in our industry impacted by the pandemic and travel restrictions in March of this year, and the organizers did a superb job of adjusting the schedule. I was able to review a DVCon tutorial called “Defining a SystemC Methodology for your Company“, given by Swaminathan Ramachandran… Read More


A Tour of This Year’s DAC IP Track with Randy Fish

A Tour of This Year’s DAC IP Track with Randy Fish
by Mike Gianfagna on 07-10-2020 at 10:00 am

Randy Fish

DAC is a complex event with many “moving parts”. While the conference has gone virtual this year (as all events have), the depth of the event remains the same. The technical program has always been of top quality, with peer-reviewed papers presented across many topics and across the world. This is also the oldest part of DAC, dating… Read More


Contact over Active Gate Process Requirements for 5G

Contact over Active Gate Process Requirements for 5G
by Tom Dillinger on 07-01-2020 at 6:00 am

frequency 5G

Summary
A recent process enhancement in advanced nodes is to support the fabrication of contacts directly on the active gate area of a device.  At the recent VLSI 2020 Symposium, the critical advantages of this capability were highlighted, specifically in the context of the behavior of RF CMOS devices needed for 5G designs.

IntroductionRead More


Optimizing Chiplet-to-Chiplet Communications

Optimizing Chiplet-to-Chiplet Communications
by Tom Dillinger on 06-29-2020 at 6:00 am

bump dimensions

Summary
The growing significance of ultra-short reach (USR) interfaces on 2.5D packaging technology has led to a variety of electrical definitions and circuit implementations.  TSMC recently presented the approach adopted by their IP development team, for a parallel-bus, clock-forwarded USR interface to optimize power/performance/area… Read More


Multi-Vt Device Offerings for Advanced Process Nodes

Multi-Vt Device Offerings for Advanced Process Nodes
by Tom Dillinger on 06-26-2020 at 6:00 am

Ion Ioff

Summary
As a result of extensive focus on the development of workfunction metal (WFM) deposition, lithography, and removal, both FinFET and gate-all-around (GAA) devices will offer a wide range of Vt levels for advanced process nodes below 7nm.

Introduction
Cell library and IP designers rely on the availability of nFET and pFET… Read More