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Three Key Takeaways from the 2022 TSMC Technical Symposium!

Three Key Takeaways from the 2022 TSMC Technical Symposium!
by Daniel Nenni on 06-16-2022 at 12:10 pm

TSMC Technology Roadmap 2022

The TSMC Technical Symposium is today so I wanted to give you a brief summary of what was presented. Tom Dillinger will do a more technical review as he has done in the past. I don’t want to steal his thunder but here is what I think are the key takeaways. First a brief history lesson.

The history of TSMC Technology Development with 12 keyRead More


Intel 4 Deep Dive

Intel 4 Deep Dive
by Scotten Jones on 06-13-2022 at 6:00 am

Figure 1

As I previously wrote about here, Intel is presenting their Intel 4 process at the VLSI Technology conference. Last Wednesday Bernhard Sell (Ben) from Intel gave the press a briefing on the process and provided us with early access to the paper (embargoed until Sunday 6/12).

“Intel 4 CMOS Technology Featuring Advanced FinFET TransistorsRead More


WEBINAR: 5G is moving to a new and Open Platform O-RAN or Open Radio Access Network

WEBINAR: 5G is moving to a new and Open Platform O-RAN or Open Radio Access Network
by Daniel Nenni on 06-10-2022 at 6:00 am

The demands of 5G requires new designs to not only save power but also increase performance and by moving to advance power-saving nodes and by using eFPGAs will help to achieve these goals. This paper will introduce 5G and O-RAN, the complexity of these systems, and how flexibility could be beneficial. Then we will dive into how eFPGA… Read More


An Update on In-Line Wafer Inspection Technology

An Update on In-Line Wafer Inspection Technology
by Tom Dillinger on 06-06-2022 at 6:00 am

inspection overview

From initial process technology development (TD) to high volume manufacturing (HVM) status for a new node, one of the key support functions to improve and maintain yield is the in-line wafer inspection technology.  Actually, there are multiple inspection technologies commonly employed, with tradeoffs in pixel resolution,… Read More


Leveraging Simulation to Accelerate the Design of Plasma Reactors for Semiconductor Etching Processes

Leveraging Simulation to Accelerate the Design of Plasma Reactors for Semiconductor Etching Processes
by Kalar Rajendiran on 06-03-2022 at 6:00 am

Etching Processes

There is no shortage of reporting on the many technological advances happening within the semiconductor industry. But sometimes it feels like we hear less in the area of semiconductor manufacturing equipment than in the design and product arenas. That doesn’t mean that there is less happening there or what is happening there … Read More


Inverse Lithography Technology – A Status Update from TSMC

Inverse Lithography Technology – A Status Update from TSMC
by Tom Dillinger on 06-02-2022 at 6:00 am

ILT mask rules

“Inverse lithography technology (ILT) represents the most significant EDA advance in the last two decades.”  Danping Peng from TSMC made that assertion at the recent SPIE Advanced Lithography + Patterning Conference, in his talk entitled:  ILT for HVM:  History, Present, and Future.  This article summarizes the highlights… Read More


Unlock first-time-right complex photonic integrated circuits

Unlock first-time-right complex photonic integrated circuits
by Raha Vafaei on 06-01-2022 at 10:00 am

EPDA overview

The capacity and energy efficiency challenges from the growing appetite for high-speed data along with advanced applications such as LIDAR and quantum computing are driving demand for increasingly large-scale photonic integrated circuits (PIC). With an ever-increasing number of components on a single photonic chip, manual… Read More


0.55 High-NA Lithography Update

0.55 High-NA Lithography Update
by Tom Dillinger on 05-31-2022 at 6:00 am

mask infrastructure 0 55

At the recent SPIE Advanced Lithography + Patterning Conference, Mark Phillips from Intel gave an insightful update on the status of the introduction of the 0.55 high numerical aperture extreme ultraviolet lithography technology.  Mark went so far as to assert that the development progress toward high-NA EUV would support … Read More


Using EM/IR Analysis for Efinix FPGAs

Using EM/IR Analysis for Efinix FPGAs
by Daniel Payne on 05-30-2022 at 10:00 am

XLR min

I’ve been following the EM/IR (Electro-Migration, IR is current and resistance) analysis market for many years now, and recently attended a presentation from Steven Chin, Sr. Director IC Engineering of Efinix, at the User2User event organized by Siemens EDA. The Tuesday presentation was in the morning at the Marriott… Read More


Die-to-Die IP enabling the path to the future of Chiplets Ecosystem

Die-to-Die IP enabling the path to the future of Chiplets Ecosystem
by Kalar Rajendiran on 05-30-2022 at 6:00 am

Die to Die Interface Figure of Merit

The topic of chiplets is getting a lot of attention these days. The chiplet movement has picked up more momentum since Moore’s law started slowing down as process technology approached 5nm. With the development cost of a monolithic SoC crossing the $500M and wafer yields of large die-based chips dropping steeply, the decision … Read More