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DAC 2021 – What’s Up with Agnisys and Spec-driven IC Development

DAC 2021 – What’s Up with Agnisys and Spec-driven IC Development
by Daniel Payne on 01-11-2022 at 10:00 am

IDesignSpec min 1

Walking the exhibit floors at DAC in December I spotted the familiar face of Anupam  Bakshi, Founder and CEO of Agnisys, so I stopped by the booth to get an update on his EDA company. My first question for him was about the origin of the company name, Agnisys, and I found at that Agni means Fire in Sanskrit, one of the five elements.

The … Read More


IBM at IEDM

IBM at IEDM
by Scotten Jones on 01-10-2022 at 6:00 am

Vertical FET process

IBM transferred their semiconductor manufacturing to GLOBALFOUNDRIES several years ago but still maintains a multibillion-dollar research facility at Albany Nanotech. IBM is very active at conferences such as IEDM and appears to have a good public relations department because they get a lot of press.

At the Litho Workshop … Read More


CES 2022 and the Electrification of Cycling

CES 2022 and the Electrification of Cycling
by Daniel Payne on 01-05-2022 at 10:00 am

bosch min

With the Omicron variant of the COVID-19 virus in the news, there have been some big corporate names withdrawing from CES ( Peleton, Super73), however the cycling innovation companies assembled once again in Las Vegas this year for CES 2022. Data from statista show the strong growth in bicycle revenues in March 2020, when the pandemic… Read More


Self-Aligned Via Process Development for Beyond the 3nm Node

Self-Aligned Via Process Development for Beyond the 3nm Node
by Tom Dillinger on 01-05-2022 at 6:00 am

TEM DoD

The further scaling of interconnect and via lithography for advanced nodes is challenged by the requirement to provide a process window that supports post-patterning critical dimension variations and mask overlay tolerances.  At the recent international Electron Devices Meeting (IEDM) in San Francisco, TSMC presented … Read More


Technology Design Co-Optimization for STT-MRAM

Technology Design Co-Optimization for STT-MRAM
by Tom Dillinger on 01-04-2022 at 6:00 am

sense amplifier

Previous SemiWiki articles have described the evolution of embedded non-volatile memory (eNVM) IP from (charge-based) eFlash technology to alternative (resistive) bitcell devices.  (link, link)

The applications for eNVM are vast, and growing.  For example, microcontrollers (MCUs) integrate non-volatile memory for … Read More


Demand for High Speed Drives 200G Modulation Standards

Demand for High Speed Drives 200G Modulation Standards
by Tom Simon on 01-03-2022 at 10:00 am

200G Modulation

Right now, the most prevalent generation of Ethernet for data centers is 400 Gbps, with the shift to 800 Gbps coming rapidly. It is expected that by 2025 there will be 25 million units of 800 Gbps shipped. Line speeds of 100G are used predominantly for 400 Gbps Ethernet – requiring 4 lanes each. Initially 800 Gbps will simply … Read More


Advanced 2.5D/3D Packaging Roadmap

Advanced 2.5D/3D Packaging Roadmap
by Tom Dillinger on 01-03-2022 at 6:00 am

SoIC futures

Frequent SemiWiki readers are no doubt familiar with the advances in packaging technology introduced over the past decade.  At the recent International Electron Devices Meeting (IEDM) in San Francisco, TSMC gave an insightful presentation sharing their vision for packaging roadmap goals and challenges, to address the growing… Read More


Webinar: AMS, RF and Digital Full Custom IC Designs need Circuit Sizing

Webinar: AMS, RF and Digital Full Custom IC Designs need Circuit Sizing
by Daniel Payne on 01-02-2022 at 10:00 am

circuit sizing min

My career started out by designing DRAM circuits at Intel, and we manually sized every transistor in the entire design to get the optimum performance, power and area. Yes, it was time consuming, required lots of SPICE iterations and was a bit error prone. Thank goodness times have changed, and circuit designers can work smarter … Read More


DAC 2021 – Cliosoft Overview

DAC 2021 – Cliosoft Overview
by Daniel Payne on 12-30-2021 at 6:00 am

Simon and Karim min

It’s been awhile since I really looked at what Cliosoft has to offer in the EDA tool space, so at the 58th DAC I stopped by their exhibit booth on Tuesday to visit with Karim Khalfan, VP of Application Engineering, and Simon Rance, VP of Marketing. Their booth had all of the hot market segments listed: Automotive, 5G, IoT, AI, … Read More


Heterogeneous Integration – A Cost Analysis

Heterogeneous Integration – A Cost Analysis
by Tom Dillinger on 12-29-2021 at 10:00 am

cost comparison

Heterogeneous integration (HI) is a general term used to represent the diverse possibilities for die technology incorporated into advanced 2.5D/3D packaging.  At the recent International Electron Devices Meeting (IEDM) in San Francisco, a team from Synopsys and IC Knowledge presented data from analyses of future potential… Read More