This blog is my second blog from this year’s Linley Fall Processor Conference. The first two blogs focused on edge inference solutions. Achronix’s discussion was much broader than just AI/ML; it was about where FPGA’s have been going and culminated with a product announcement preview. I’ll get to the announcement in a moment, … Read More
BittWare PCIe server card employs high throughput AI/ML optimized 7nm FPGA
Back in May I wrote an article on the new Speedster7t from Achronix. This chip brings together Network on Chip (NoC) interconnect, high speed Ethernet and memory connections, and processing elements optimized for AI/ML. Speedster7t is a very exciting new FPGA that can be used effectively to accelerate a wide range of processing… Read More
Efficiency – Flex Logix’s Update on InferX™ X1 Edge Inference Co-Processor
Last week I attended the Linley Fall Processor Conference held in Santa Clara, CA. This blog is the first of three blogs I will be writing based on things I saw and heard at the event.
In April, Flex Logix announced its InferX X1 edge inference co-processor. At that time, Flex Logix announced that the IP would be available and that a chip,… Read More
Free webinar – Accelerating data processing with FPGA fabrics and NoCs
FPGAs have always been a great way to add performance to a system. They are capable of parallel processing and have the added bonus of reprogramability. Achronix has helped boost their utility by offering on-chip embedded FPGA fabric for integration into SoCs. This has had the effect of boosting data rates through these systems… Read More
Acceleration in a Heterogenous Compute Environment
Heterogenous compute isn’t a new concept. We’ve had it in phones and datacenters for quite a while – CPUs complemented by GPUs, DSPs and perhaps other specialized processors. But each of these compute engines has a very specific role, each driven by its own software (or training in the case of AI accelerators). You write software… Read More
AI Inference at the Edge – Architecture and Design
In the old days, product architects would throw a functional block diagram “over the wall” to the design team, who would plan the physical implementation, analyze the timing of estimated critical paths, and forecast the signal switching activity on representative benchmarks. A common reply back to the architects was, “We’ve… Read More
Learn About Implementing SmartNICs, an Achronix White Paper
We have all seen the announcements to provide ever-increasing network capabilities within the data centers. Enabling these advances are improvements in connectivity including SerDes, PAM4, optical solutions, and many others. It seems 40G is old news now, and the current push is for 400G – things are changing very quickly.… Read More
Webinar: Using Embedded FPGA to Improve Machine Learning SOCs
By its very definition, machine learning (ML) hardware requires flexibility. In turn, each ML application has its own fine grain requirements. Specific hardware implementations that include specialized processing elements are often desirable for machine learning chips. At the top of the priority list is parallel processing.… Read More
eFPGA – What a great idea! But I have no idea how I’d use it!
eFPGA stands for embedded Field Programmable Grid Arrays. An eFPGA is a programmable device like an FPGA but rather than being sold as a completed chip it is licensed as a semiconductor IP block. ASIC designers can license this IP and embed it into their own chips adding the flexibility of programmability at an incremental cost.… Read More
An evolution in FPGAs
Why does it seem like current FPGA devices work very much like the original telephone systems with exchanges where workers connected calls using cords and plugs? Achronix thinks it is now time to jettison Switch Blocks and adopt a new approach. Their motivation is to improve the suitability of FPGAs to machine learning applications,… Read More
Weebit Nano Brings ReRAM Benefits to the Automotive Market