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SNPS1610371395 synopsys ai semiwiki ads 800x100 px 
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Synopsys
Posted on

Yawn… New EDA Leader Results Are Coming

Yawn… New EDA Leader Results Are Coming
by Randy Smith on 01-18-2013 at 4:00 pm
Categories: Cadence, EDA, Siemens EDA, Synopsys

We will soon start to see the quarterly financial reporting installments of the “Big 3” public EDA companies. I predict they will be as boring as usual. I am not sure if I would want it any differently though.

Back in the 90s there were times when it was truly interesting to wait to see what Cadence, Mentor, or later Synopsys, might announce.… Read More

Posted on

Integrating your SoC into the analog world

Integrating your SoC into the analog world
by Don Dingee on 01-02-2013 at 7:00 pm
Categories: EDA, Synopsys

Our world is decidedly analog, made up of stimuli for our five basic senses of sight, touch, hearing, taste, and smell, and more advanced senses like balance and acceleration. To be effective on the Internet of Things, digital devices must integrate with the analog world, interfacing with sensors and control elements.… Read More

Posted on

The Semiconductor Landscape – II

The Semiconductor Landscape – II
by Pawan Fangaria on 01-01-2013 at 9:15 pm
Categories: EDA, GlobalFoundries, Synopsys

It has been a year since my article Semiconductor Landscape in Jan 2012 I wanted to look back into the major events over the year and then anticipate what’s in store going forward. What has happened over the year is much more than what I could foresee. Major consolidation in EDA space – Synopsys acquired Magma, SpringSoft, Ciranova,… Read More

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FinFET Modeling and Extraction at 16-nm

FinFET Modeling and Extraction at 16-nm
by Daniel Payne on 12-18-2012 at 12:05 pm
Categories: EDA, FinFET, Synopsys

In 2012 FinFET is one of the most talked about MOS technologies of the year because traditional planar CMOS has slowed down on scaling below the 28nm node. To learn more about FinFET process modeling I attended a Synopsys webinar where Bari Biswas presented for about 42 minutes include a Q&A portion at the end.


Bari Biswas, Synopsys… Read More

Posted on

A Brief History of Synopsys

A Brief History of Synopsys
by Daniel Nenni on 12-12-2012 at 1:00 pm
Categories: EDA, Synopsys

One of the largest software companies in the world, Synopsys is a market and technology leader in the development and sale of electronic design automation (EDA) tools and semiconductor intellectual property (IP). Synopsys is also a strong supporter of local education through the Synopsys Outreach Foundation. Each year in multiple… Read More

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Double Patterning Verification

Double Patterning Verification
by Paul McLellan on 12-10-2012 at 3:03 am
Categories: EDA, Synopsys

You can’t have failed to notice that 20nm is coming. There are a huge number of things that are different about 20nm from 28nm, but far and away the biggest is the need for double patterning. You probably know what this is by now, but just in case, here is a quick summary.

Lithography is done using 193nm light. Today we use immersion… Read More

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Second FPGA to the right, and straight on ‘til it works

Second FPGA to the right, and straight on ‘til it works
by Don Dingee on 11-26-2012 at 6:00 pm
Categories: EDA, FPGA, Synopsys

In a fantasy world where there were no coding errors or integration issues, FPGA designs would fly straight through synthesis easily and quickly. Maybe that world does exist somewhere. For the rest of us, who have experienced the agony of running a large FPGA design – again – only to find another error and have to start over, there … Read More

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Next Generation FPGA Prototyping

Next Generation FPGA Prototyping
by Paul McLellan on 11-12-2012 at 7:00 am
Categories: EDA, FPGA, Synopsys

One technology that has quietly gone mainstream in semiconductor design is FPGA prototyping. That is, using an FPGA version of the design to run extensive verification. There are two approaches to doing this. The first way is simply to build an prototype board, buy some FPGAs from Xilinx or Altera and do everything yourself. The… Read More

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Static Timing Analysis for Memory Characterization

Static Timing Analysis for Memory Characterization
by Daniel Payne on 11-11-2012 at 6:18 pm
Categories: EDA, Synopsys

Modern SoC (System On Chip) designs contain a larger number of RAM (Random Access Memory) instances, so how do you know what the speed, timing and power are for any instance? There are a couple of approaches:
[LIST=1]

  • Trust the IP supplier to give you models that use polynomial equations to curve-fit the performance numbers based
    • … Read More