Now and again, I enjoy circling back to a topic on which I spent a good deal of time back in my Atrenta days – clock domain crossing analysis (CDC). This is an area that still has opportunity to surprise me at least, in this case looking at CDC analysis around MBIST logic. CDC for MBIST might seem strange. Isn’t everything in test mode synchronous… Read More
Electronic Design Automation
S2C EDA Delivers on Plan to Scale-Up FPGA Prototyping Platforms to Billions of Gates
S2C has been a global leader in FPGA prototyping for nearly two decades now, and its FPGA prototyping platforms have closely tracked the availability of the latest FPGAs – including the latest FPGAs from both Xilinx and Intel. And they are definitely delivering on the promise to advance their prototyping solutions for hyperscale… Read More
Cliosoft Webinar: What’s Needed for Next Generation IP-Based Digital Design
There’s plenty of talk about requirements for IP data management. The fundamental methods to prevent chaos, waste or worse are popular topics. I’ve covered webinars from Cliosoft on the topic on SemiWiki. But what about the future? What’s really needed to set up a path that scales, addressing the challenges of today and the new … Read More
Back to Basics in RTL Design Quality
Harry Foster waxes philosophical in a recent white paper from Siemens EDA, in this case on the origins of bugs and the best way to avoid them. Spoiler alert, the answer is not to make them in the first place or at least to flush them out very quickly. I’m not being cynical – that really is the answer though practice often falls short of ideal.… Read More
Latest Updates to Altair Accelerator, the Industry’s Fastest Enterprise Job Scheduler
Altair is a broad-based company that delivers critical enabling technology across many disciplines that will be familiar to SemiWiki readers. According to its website, Altair delivers open-architecture solutions for data analytics & AI, computer-aided engineering, and high-performance computing (HPC). You can learn… Read More
Lecture Series: Designing a Time Interleaved ADC for 5G Automotive Applications
A recent educational virtual event with the above title was jointly sponsored by Synopsys and Global Foundries. The objective was to bring awareness to state-of-the-art mixed-signal design practices for automotive circuits. The 2-day event comprised of lectures delivered by engineering professors and doctoral students… Read More
Optical I/O Solutions for Next-Generation Computing Systems
According to DARPA the fraction of total power consumed in semiconductors for I/O purposes as been growing rapidly and is creating an I/O power bottleneck. It has reached the point where it needs to be addressed with new technologies and approaches. Interestingly, while the energy density, as measured by pJ/bit for short reach… Read More
Memory Consistency Checks at RTL. Innovation in Verification
Multicore systems working with shared memory must support a well-defined model for consistency of thread accesses to that memory. There are multiple possible consistency models. Can a design team run memory consistency checks at RTL? Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur,… Read More
Webinar: A Practical Approach to FinFET Layout Automation That Really Works
There are certain tasks that have been the holy grail of EDA for some time. A real silicon compiler – high level language as input and an optimal, correct layout as output is one. Fully automated analog design – objectives as input, optimal circuit as output is another. With the increased layout times, due to the ever-increasing design… Read More
Cadence Reveals Front-to-Back Safety
This is another level-up story, a direction I am finding increasingly appealing. This is when a critical supplier in the electronics value chain moves beyond islands of design automation to provide an integrated solution for the front-to-back design for capabilities now essential for automotive and industrial automation … Read More
A Quick Tour Through Prompt Engineering as it Might Apply to Debug