Banner Electrical Verification The invisible bottleneck in IC design updated 1
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ISSCC 2012: Silicon Systems for Sustainability!

ISSCC 2012: Silicon Systems for Sustainability!
by Daniel Nenni on 02-26-2012 at 4:00 pm


What can we do for Earth’s sustainability? Besides sorting our garbage and recycling our lawn clippings? Sustainability must be the paramount theme for the future of human society! Semiconductors for a better life! Well, according to my kids, if you take away their smart phones there is no life!… Read More


Synopsys at DVCon: tutorial, lunch, keynote, exhibits and more

Synopsys at DVCon: tutorial, lunch, keynote, exhibits and more
by Paul McLellan on 02-24-2012 at 1:10 pm

DVCon is next week, which I’m sure you know already if you are in verification. Of course Synopsys has a rich product portfolio in verification and verification IP (VIP) so is pretty visible at the show.

On Wednesday they are sponsoring lunch. Several Synopsys customers will talk about their view of how the verification landscape… Read More


Call for Papers: International Gathering for Application Developers!

Call for Papers: International Gathering for Application Developers!
by Daniel Nenni on 02-22-2012 at 8:40 pm

SemiWiki would like to call you, your co-workers, and your company to participate at ERSA Conference in Las Vegas , July 16-19, 2012. I will be there and it would be a pleasure to work with you on this very important event!

ERSA, is Engineering of Reconfigurable Systems and Algorithms. Since this year, the emphasis will be on the commercialRead More


Seminar on IC Yield Optimization at DATE on March 14th

Seminar on IC Yield Optimization at DATE on March 14th
by Daniel Payne on 02-22-2012 at 3:59 pm

My first chip design at Intel was a DRAM and we had a 5% yield problem caused by electromigration issues, yes, you can have EM issues even with 6um NMOS technology. We had lots of questions but precious few answers on how to pinpoint and eliminate the source of yield loss. Fortunately, with the next generation of DRAM quickly introduced… Read More


Custom Processors: Webinar

Custom Processors: Webinar
by Paul McLellan on 02-21-2012 at 5:24 pm

What is a custom processor? Or Application Specific Instruction-set Processor (ASIP) which is the buzzword which may or may not catch on.

Most programming is done on a processor with a fixed instruction set: think Intel x86 or ARM. Intel or ARM decided on what instructions to include, based on a lot of benchmarking across a wide range… Read More


Pinpoint: Getting Control of Design Data

Pinpoint: Getting Control of Design Data
by Paul McLellan on 02-20-2012 at 5:39 pm

Back in the Napoleonic era it was possible to manage a battle with very ad hoc methods. Sit on a horse on top of the highest hill and watch the battle unfold, send messengers out with instructions. By the First World War, never mind the second, that approach was hopelessly outdated and a much more structured way of managing a battle was… Read More


Multicore SoC Architecture Optimization

Multicore SoC Architecture Optimization
by Eric Esteve on 02-16-2012 at 5:36 am

Once again with Synopsys and Arteris, the innovation is coming to solve an issue, faced by their potential customers: “In our research, we’ve found that almost half of project delays are caused by problems with the system architecture design and specification,” said Chris Rommel, vice president, embedded… Read More


Words of AMS Wisdom from the Developer of Spectre, Spectre RF, Verilog-A, Verilog-AMS

Words of AMS Wisdom from the Developer of Spectre, Spectre RF, Verilog-A, Verilog-AMS
by Daniel Payne on 02-15-2012 at 10:27 am

Ken Kundert while at Cadence developed: Spectre, Spectre RF, Verilog-A and Verilog-AMS. About 6 years ago he and Henry Chang left Cadence and created a consulting company called The Designers Guide.
Read More