ads mdx semiwiki building trust gen 800x100ai
WP_Term Object
(
    [term_id] => 157
    [name] => EDA
    [slug] => eda
    [term_group] => 0
    [term_taxonomy_id] => 157
    [taxonomy] => category
    [description] => Electronic Design Automation
    [parent] => 0
    [count] => 4278
    [filter] => raw
    [cat_ID] => 157
    [category_count] => 4278
    [category_description] => Electronic Design Automation
    [cat_name] => EDA
    [category_nicename] => eda
    [category_parent] => 0
    [is_post] => 
)
EDA

Electronic Design Automation

Posted on

Advanced Memory Cell Characterization with Calibre xACT 3D

Advanced Memory Cell Characterization with Calibre xACT 3D
by SStalnaker on 01-12-2012 at 7:18 pm
Categories: EDA, Siemens EDA

Advanced process technologies for manufacturing computer chips enable more functionality, higher performance, and low power through smaller sizes. Memory bits on a chip are predicted to double every two years to keep up with the demand for increased performance.

To meet these new requirements for performance and power, memory… Read More

Posted on

Memory Controller IP, battle field where Cadence and Synopsys are really fighting face to face. Today let’s have a look at Cadence’s strategy.

Memory Controller IP, battle field where Cadence and Synopsys are really fighting face to face. Today let’s have a look at Cadence’s strategy.
by Eric Esteve on 01-12-2012 at 9:45 am
Categories: Cadence, IP

I have shared with you last year some strategic information released by Cadence in April about their IP strategy, more specifically about the launch of the DDR4 Controller IP. And try to understand Cadence strategy about Interface IP in general (USB, PCIe, SATA, DDRn, HDMI, MIPI…) and how Cadence is positioned in respect with their… Read More

Posted on

Speeding SoC timing closure

Speeding SoC timing closure
by Paul McLellan on 01-12-2012 at 1:42 am
Categories: EDA

As chips have become larger, one of the more challenging steps is full-chip signoff. Lots of other steps in the design process can work on just a part of the problem, but by definition full-chip signoff has to work on the full chip. But it is not just that chips have got larger, the number of corners that need to be validated has also exploded.… Read More

Posted on

Imera Virtual Fabric

Imera Virtual Fabric
by Paul McLellan on 01-10-2012 at 6:00 am
Categories: EDA

Virtual fabric sounds like something that would be good for making the emperor’s new clothes. I talked today to Les Spruiell of Imera to find out what it really is.

Anyone who has worked as either a designer or as an EDA engineer has had the problem of a customer who has a problem but can’t send you the design since it is (a)… Read More

Posted on

Synopsys, the first 25 years

Synopsys, the first 25 years
by Paul McLellan on 01-08-2012 at 8:00 pm
Categories: EDA, Synopsys

Synopsys was started in 1986 and so 2011 was its 25th anniversary. They created a little timeline with some of their history. As with most companies, the earlier history is the most interesting, before it was clear what the future would bring. From 1986 to 1990 they grew to $22M in revenue, which was explosive growth. So explosive … Read More

Posted on

VLSI 2012 in Hyderabad

VLSI 2012 in Hyderabad
by Paul McLellan on 01-06-2012 at 3:59 pm
Categories: EDA

Atrenta will be on a panel session at VLSI 2012 next week in Hyderabad in the center of India. Since I had a development group there over a decade ago this is actually one of the few cities in India that I have visited. Beautiful but very hot at the time I was there.

Atrenta will be represented by Sathyam Pattanam the director of engineering… Read More

Posted on

EDA Vendors Providing Secure Remote Support for an IC Design Flow

EDA Vendors Providing Secure Remote Support for an IC Design Flow
by Daniel Payne on 01-05-2012 at 5:38 pm
Categories: EDA, Siemens EDA

In my last corporate EDA job I had customers in Korea that were evaluating a new circuit simulator and getting strange results. When I asked, “Could you send me your test case?” the reply was always, “No, we cannot let any of our IC design data leave the building because of security concerns.”… Read More

Posted on

What Will 2012 Bring The Semiconductor Ecosystem?

What Will 2012 Bring The Semiconductor Ecosystem?
by Daniel Nenni on 12-18-2011 at 4:30 pm
Categories: EDA

During my annual holiday meal with one of my favorite EDA icons some rather bold predictions were made. On his side it was more of what he would LIKE to see happen, on my side it was more of what will HAVE to happen for the semiconductor ecosystem to thrive in the coming years.

Mike Gianfagna (Viva Italia!) spent 15+ years with RCA/GE Semiconductor… Read More

Posted on

Clock Design for SOCs with Lower Power and Better Specs

Clock Design for SOCs with Lower Power and Better Specs
by Daniel Payne on 12-15-2011 at 5:03 pm
Categories: EDA, General

Dan Ganousis posted in our SemiWiki forums about a newer technique to lower the power consumed by GHz clocks on SOC designs and asked if I was interested to learn more, so we met today via WebEx. Dan is with a company called Cyclos Semiconductor, co-founded in 2006 by Marios Papaefthymiou, President and Alexander Ishii, VP of Engineering.… Read More