SNPS1670747138 DAC 2025 800x100px HRes
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EDA

Electronic Design Automation

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Circuit Simulation and IC Layout update from Mentor at DAC

Circuit Simulation and IC Layout update from Mentor at DAC
by Daniel Payne on 06-17-2011 at 7:06 pm
Categories: EDA, Siemens EDA

Intro
On Monday evening I talked with Linda Fosler, Director of marketing for the DSM Division at Mentor about what’s new at DAC this year in circuit simulation and IC layout tools.

Notes
IC Station – old name for IC layout tools

Eldo – Eldo Classic- Cell characterization
– ST is the early customer and teaching customer,… Read More

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An Affordable 3D Field Solver at DAC

An Affordable 3D Field Solver at DAC
by Daniel Payne on 06-17-2011 at 6:35 pm
Categories: EDA, Tanner EDA

Intro
Massimo Sivilotti, Ph.D of Tanner EDA showed me their 3D field solver in the HiPer PX extraction tool at DAC last week.

Notes

Tool Suites – schematics, layout, SPICE simulation, DRC/LVS
– HiPer PX: 3D Field solvero Layers, dielectrics,
o Finite element analysis
o Boundary element methods
o 2D mode for pattern matching… Read More

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Hardware Configuration Management at DAC

Hardware Configuration Management at DAC
by Daniel Payne on 06-17-2011 at 6:20 pm
Categories: Cliosoft, EDA

Intro
Show me what has changed in my RTL or Schematic since the last time I looked. This task is now automated by Cliosoft with their new hierarchical tool called Visual Design Difference (VDD). Srinath showed me what was new for DAC.


Srinath Anantharaman

Notes
LSI, STMicro – use DesignSync for their DM but use VDD for seeing visual… Read More

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EDA Interoperability at DAC

EDA Interoperability at DAC
by Daniel Payne on 06-17-2011 at 4:42 pm
Categories: EDA, Synopsys

Intro
My Wednesday breakfast at DAC last week was at the Interoperability event sponsored by Synopsys. The Synopsys moderator was so jovial that he reminded me of Jerry Lewis, I was relieved when the guests gave us an update.

Notes
Interconnect Modeling- Open Source Interconnect Technology Format (ITF)o Used by Star RC

–… Read More

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Synopsys IC Validator at DAC

Synopsys IC Validator at DAC
by Daniel Payne on 06-14-2011 at 3:14 pm
Categories: EDA, Synopsys

Intro
At DAC last week I visited the Synopsys demo suite to see what’s new with IC Validator.


Notes
Stelios Diamantidis, PMM
– In-design physical verification
– Sign-off reveals thousands of late stage DRC violations
– 28nm has 1.5K rules, 15K runset sizes
– Metal Fill changes timing
– The… Read More

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Tanner EDA at DAC

Tanner EDA at DAC
by Daniel Payne on 06-14-2011 at 2:40 pm
Categories: EDA, Tanner EDA

Intro
For 22 years now Tanner EDAhas been in the business pf offering tools for AMS and MEMS designers. I learned what’s new at DAC on Tuesday morning.

Notes
Nicholas Williams – Director of Product Management

Tanner EDA front end: S-Edit integrates with Berkeley Fast Analog Simulator
W-Edit – is the waveform viewer

Who is … Read More

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A Birds-Eye Overview of DRC+

A Birds-Eye Overview of DRC+
by Daniel Nenni on 06-13-2011 at 10:57 pm
Categories: EDA, Foundries, GlobalFoundries

The GlobalFoundries DRC+ platform is one of the most innovative DFM technologies and was well represented at #48DAC. In case you missed it, here is a reprint of a DRC+ overview from GFI just prior to #48DAC:

DRC (Design Rule Constraints) are the fundamental principles in constraining VLSI (Very Large Scale Integration) circuit… Read More

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HSPICE gets Faster, better Convergence

HSPICE gets Faster, better Convergence
by Daniel Payne on 06-13-2011 at 5:53 pm
Categories: EDA, Synopsys

Hany El Hak – Product Marketing Manager

Frederik Iverson – AE

Scott Wetch – HSPICE Architect

HSPICE – 5 years ago convergence was not so good, while 95% of analog circuits today converge out of the box, no options are required.

Synopsys AMS Portfolio – wide range of tools
– Custom Designer: IC schematic and layout tools
–… Read More

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Nimbic (formerly Physware) – 3D Field Solver in the Cloud or Desktop

Nimbic (formerly Physware) – 3D Field Solver in the Cloud or Desktop
by Daniel Payne on 06-13-2011 at 12:57 pm
Categories: EDA, Siemens EDA

I met with Bala Vishwanath, CMO at Nimbic on Monday morning. They had just announced a $6.9M round of venture capital which is something that you rarely hear about in EDA these days, especially during a slow economic recovery.

Intro

Physware – served the package and board markets, co-design challenges (can add IC noise sources).… Read More