Webinar 800x100 (1)
WP_Term Object
(
    [term_id] => 157
    [name] => EDA
    [slug] => eda
    [term_group] => 0
    [term_taxonomy_id] => 157
    [taxonomy] => category
    [description] => Electronic Design Automation
    [parent] => 0
    [count] => 3908
    [filter] => raw
    [cat_ID] => 157
    [category_count] => 3908
    [category_description] => Electronic Design Automation
    [cat_name] => EDA
    [category_nicename] => eda
    [category_parent] => 0
    [is_post] => 
)
EDA

Electronic Design Automation

Posted on

AMS Simulation Update from Mentor Graphics at DAC

AMS Simulation Update from Mentor Graphics at DAC
by Daniel Payne on 06-25-2012 at 12:36 pm
Categories: EDA, Siemens EDA
6 Comments

I met with Jay Madiraju of Mentor Graphics on Wednesday at DAC to get an update on their AMS simulation products. We worked together at Mentor back when Mach TA was being developed as a Fast SPICE circuit simulator.… Read More

Posted on

FinFET Standard Cells at DAC

FinFET Standard Cells at DAC
by Daniel Payne on 06-25-2012 at 11:45 am
Categories: EDA, Events, IP

Rajiv Bhateja, Dhrumil Gandhi and Neal Carney met with me at DAC on Wednesday to give an update on what’s new in 2012 for Tela Innovations, a provider of lithography optimized IP and tools. This team has a rich history in EDA and IP from companies like: ARM, Artisan, Mentor Graphics and Silicon Compilers.… Read More

Posted on

TSMC Theater Presentation: Apache

TSMC Theater Presentation: Apache
by Paul McLellan on 06-25-2012 at 12:13 am
Categories: Ansys, Inc., EDA

At the TSMC Theater Apache (don’t forget, now a subsidary of Ansys) talked about Emerging Challenges for Power, Signal and Reliability Verification on 3D-IC and Silicon Interposer Designs. The more I see about the costs and challenges of 20/22nm and below, the more I think that these 3D and 2.5D approaches are going to be … Read More

Posted on

Finding RTL Bugs Live Using Formal Techniques

Finding RTL Bugs Live Using Formal Techniques
by Daniel Payne on 06-24-2012 at 8:10 pm
Categories: EDA, Events

Most of what you see at DAC is canned PowerPoint presentations, however on Tuesday afternoon I spotted a company called Oski Technology that was doing something almost unheard of – they had an engineer debugging a digital design from Nvidia using formal tools live. I later found out the engineer found 4 bugs in just three days… Read More

Posted on

DesignSync update from Dassault Systems at DAC

DesignSync update from Dassault Systems at DAC
by Daniel Payne on 06-24-2012 at 8:10 pm
Categories: Dassault Systemes, EDA

At DAC on Wednesday Rick Stanton of Dassault Systems gave me an update on what’s new with DesignSync, a design data management tool offered since 1998. Rick and I both worked at Viewlogic in the 90’s along with Dennis Harmon who then founded Synchronicity, later acquired by Dassault Systems.… Read More

Posted on

Webinar: how to reduce mobile device cost and board space with LLI

Webinar: how to reduce mobile device cost and board space with LLI
by Eric Esteve on 06-24-2012 at 2:46 am
Categories: Arteris, EDA, IP, Synopsys

LLI Specification has been officially released by the MIPI Alliance, at the occasion of the Mobile World Congress in Barcelona, this year. As indicated by the name, the round-trip latency of the LLI inter-chip connection is fast enough for a mobile phone modem to share an application processor’s memory while maintaining… Read More