SILVACO 073125 Webinar 800x100
WP_Term Object
(
    [term_id] => 157
    [name] => EDA
    [slug] => eda
    [term_group] => 0
    [term_taxonomy_id] => 157
    [taxonomy] => category
    [description] => Electronic Design Automation
    [parent] => 0
    [count] => 4182
    [filter] => raw
    [cat_ID] => 157
    [category_count] => 4182
    [category_description] => Electronic Design Automation
    [cat_name] => EDA
    [category_nicename] => eda
    [category_parent] => 0
    [is_post] => 
)
EDA

Electronic Design Automation

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Costello on Story Telling

Costello on Story Telling
by Paul McLellan on 05-01-2013 at 9:03 pm
Categories: EDA, Events

Last night at Cadence was the next installment of what I have been calling Hogan University. Jim interviewed Joe Costello about how to tell a story as part of the EDAC emerging companies series of events. The main focus was how to tell a story as a small EDA company communicating with investors, although there are obviously other forms… Read More

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DAC: Calypto Insight Presentation

DAC: Calypto Insight Presentation
by Paul McLellan on 05-01-2013 at 5:39 pm
Categories: EDA

DAC has several “Insight Presentations” on Wednesday June 5th. Bryan Bowyer from Calypto will be presenting from 2-4pm that day (don’t know where, the DAC website doesn’t have a room number specified yet). The topic is Reducing Design and Debug Time with Synthesizable TLM. TLM, of course, stands for… Read More

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DAC Keynotes: 5 This Year

DAC Keynotes: 5 This Year
by Paul McLellan on 05-01-2013 at 2:38 pm
Categories: EDA, Events

DAC is in Austin this year, as I’m sure you know, and DAC has keynotes by CEOs of two Austin-based companies Freescale Semiconductor and National Instrument. Two more keynotes (one split into two) are focused on mobile, which has become the major driver of semiconductor today. A fifth keynote, including presentation of … Read More

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Accelerating Design Debug in an ASIC Prototype

Accelerating Design Debug in an ASIC Prototype
by Daniel Nenni on 04-30-2013 at 8:15 pm
Categories: EDA

ASIC prototyping in FPGAs is starting to trend on SemiWiki. As FPGA technology becomes more advanced customers tell me that the traditional debug tools are inadequate. Faced with the very restrictive debugging capabilities and very long synthesis/place/route times the debugging cycle in these prototype platforms are quite… Read More

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Crossfire – Builds Quality with Design

Crossfire – Builds Quality with Design
by Pawan Fangaria on 04-30-2013 at 8:05 pm
Categories: EDA, Fractal Technologies

Very often we talk about increasing design complexities and verification challenges of SoCs. With ever growing design sizes and multiple IPs on a single SoC, it’s a fact that SoC design has become heterogeneous, being developed by multiple teams, either in-house or outsourced. Considering economic advantage amid pressure … Read More

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A Programmable Electrical Rule Checker

A Programmable Electrical Rule Checker
by Daniel Payne on 04-29-2013 at 11:21 pm
Categories: EDA

IC designers involved with physical design are familiar with acronyms like DRC (Design Rule Check), LVS (Layout Versus Schematic) and DFM (Design For Manufacturing), but how would you go about checking for compliance with ESD (Electro Static Discharge) rules? You may be able to kludge something together with your DRC tool and… Read More

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Hot Topic – CMOS Image Sensor Verification!

Hot Topic – CMOS Image Sensor Verification!
by Daniel Nenni on 04-29-2013 at 7:30 pm
Categories: EDA

Mobile applications require CMOS image sensor devices that have a low signal-to-noise ratio (SNR), low power, small area, high resolution, high dynamic range, and high frame rate. CMOS image sensor imaging performance is noise limited requiring accurate noise analysis on the pixel array electronics and column readout circuitry.… Read More

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Beyond one FPGA comfort zone

Beyond one FPGA comfort zone
by Don Dingee on 04-29-2013 at 5:00 pm
Categories: Aldec, EDA, FPGA

Unless you are a small company with one design team, the chance you have standardized on one FPGA vendor for all your needs, forever and ever, is unlikely. No doubt you probably have a favorite, because of the specific class of part you use most often or the tool you are most familiar with, but I’d bet you use more than one FPGA vendor routinely.… Read More

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Transient Noise Analysis (TNA)

Transient Noise Analysis (TNA)
by Rupindermand on 04-29-2013 at 4:21 pm
Categories: EDA, Tanner EDA

Tanner EDA Applications Engineers see a broad range of technical challenges that our users are trying to overcome. Here’s one worth sharing – it deals with transient noise analysis (TNA) for a comparator design. The customer is a producer of advanced flow measurement devices for application in medicine and research. The designer… Read More

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Challenges of 20nm IC Design

Challenges of 20nm IC Design
by Daniel Payne on 04-29-2013 at 11:38 am
Categories: EDA, Synopsys

Designing at the 20nm node is harder than at 28nm, mostly because of the lithography and process variability challenges that in turn require changes to EDA tools and mask making. The attraction of 20nm design is realizing SoCs with 20 billion transistors. Saleem Haider from Synopsys spoke with me last week to review how Synopsys… Read More