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EDA

Electronic Design Automation

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Designing Power Management ICs

Designing Power Management ICs
by Paul McLellan on 09-20-2013 at 5:49 pm
Categories: EDA, Synopsys

With all the focus in design on SoCs in the latest sexy process (Hi-K Metal Gate! FinFETs!) it is easy to forget all the other chips that go into a system. When we say “system on a chip” there are actually very few systems that really get everything onto a single chip. One of the big areas that usually cannot go on the latest… Read More

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Who is Blogging at Cadence?

Who is Blogging at Cadence?
by Daniel Payne on 09-20-2013 at 1:31 pm
Categories: Cadence, EDA

As a blogger in the EDA industry I get to write every week, however I also end up reading every blog on SemiWiki plus multiple other sites to keep current on what’s happening in our business. I thought that it would be informative to look at Cadence Design Systems and how they are using blogging to talk not just about their own EDA… Read More

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Process Variation is a Yield Killer!

Process Variation is a Yield Killer!
by Daniel Nenni on 09-20-2013 at 11:00 am
Categories: EDA, Solido

With the insatiable wafer appetites of the fabless semiconductor companies in the mobile space, yield has never been more critical. The result being better EDA tools every year and this blog highlights one of the many examples. It has been a pleasure writing about Solido Design Automation and seeing them succeed amongst the foundries… Read More

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Interface PHY IP supporting Mobile Application on TSMC 20nm? Available!

Interface PHY IP supporting Mobile Application on TSMC 20nm? Available!
by Eric Esteve on 09-20-2013 at 8:42 am
Categories: IP, Synopsys

If we check the many articles daily published in Semiwiki, I am sure that Moore’s Law has been mentioned every single day. There is a good reason why we constantly write about new technologies and advanced features like FinFet, FD-SOI, 450 mm wafers or double patterning: all of these are new challenges that the SC industry will have… Read More

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What’s in your network processor?

What’s in your network processor?
by Don Dingee on 09-19-2013 at 8:00 pm
Categories: EDA, Siemens EDA

Recently, one of those very restrained press releases – in this case, Mentor Graphics and Imagination Technologiesextending their partnership for MIPS software support– crossed my desk with about 10% of the story. The 90% of this story I want to focus on is why Mentor is putting energy into this partnership… Read More

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Cutting Debug Time of an SoC

Cutting Debug Time of an SoC
by Daniel Payne on 09-19-2013 at 2:26 pm
Categories: EDA

The amount of time spent debugging an SoC dwarfs the actual design time, with many engineering teams saying that debug and verification takes about 7X the effort as the actual design work. So any automation to reduce the amount of time spent in debug and verification would directly impact the product schedule in a big way.

An example… Read More

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A Brief History of Magillem

A Brief History of Magillem
by Daniel Payne on 09-19-2013 at 1:17 pm
Categories: EDA, Magillem

Founders

Cyril Spasevski is the President, CTO and founding engineer at Magillem, bringing a team of engineers, all experts with an SoC platform builder tool. In 2006 Cyril and his team met a seasoned business woman, and decided to form Magillem. Design teams were struggling with different tools at different stages of the flow,… Read More

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Early Test –> Less Expensive, Better Health, Faster Closure

Early Test –> Less Expensive, Better Health, Faster Closure
by Pawan Fangaria on 09-18-2013 at 11:00 am
Categories: EDA


I am talking about the health of electronic and semiconductor design, which if made sound at RTL stage, can set it right for the rest of the design cycle for faster closure and also at lesser cost. Last week was the week of ITC(International Test Conference) for the Semiconductor and EDA community. I was looking forward to what ITC… Read More

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Mentor Teaches Us About the Higg’s Boson

Mentor Teaches Us About the Higg’s Boson
by Paul McLellan on 09-17-2013 at 4:46 pm
Categories: EDA, Siemens EDA

Once a year Mentor has a customer appreciation event in Silicon Valley with a guest speaker on some aspect of science. This is silicon valley, after all, so we all have to be geeks. This year it was Dr Sean Carroll from CalTech on The Particle at the End of the Universe, the Hunt for The Higg’s Boson and What’s Next.

Wally … Read More

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EDAC Export Seminar: Don’t Know This Stuff…Go Directly to Jail…Do Not Pass Go

EDAC Export Seminar: Don’t Know This Stuff…Go Directly to Jail…Do Not Pass Go
by Paul McLellan on 09-17-2013 at 2:04 pm
Categories: EDA

I am not making this up: All exports from the United States of EDA software and services are controlled under the Export Administration Regulations, administered by the U.S. Department of Commerce’s Bureau of Industry and Security (BIS). You need to understand these regulations. Failure to comply can result in severe … Read More