CAST Compression IP Webinar 800x100 (2)
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FinFET & Multi-patterning Need Special P&R Handling

FinFET & Multi-patterning Need Special P&R Handling
by Pawan Fangaria on 04-28-2014 at 1:00 pm

I think by now a lot has been said about the necessity of multi-patterning at advanced technology nodes with extremely low feature size such as 20nm, because lithography using 193nm wavelength of light makes printing and manufacturing of semiconductor design very difficult. The multi-patterning is a novel semiconductor manufacturing… Read More


Dr. Bernard Murphy: My presentation at EDPS 2014

Dr. Bernard Murphy: My presentation at EDPS 2014
by Daniel Nenni on 04-28-2014 at 8:00 am

First, I wish there were more conferences/workshops like this. This is much more about sharing ideas and brainstorming than the stark commercialism of DAC. I presented Atrenta’s role in enabling 3[SUP]rd[/SUP]-party IP qualification for the TSMC soft IP library.

My presentation slides are located here:

http://www.eda.org/edps/Papers/5-3%20Bernard%20Murphy.pdfRead More


Secret of TI’s Success in Analog & Embedded Space

Secret of TI’s Success in Analog & Embedded Space
by Pawan Fangaria on 04-27-2014 at 7:30 am

Since I started looking at the ways Texas Instrumentsworks through its strategies, my belief is getting firmed up that this is one company which can always sail through rough waters during downturn and reap rich benefits during upturn. They regularly review their strategies and can predict ahead of time when the water is about … Read More


Webinar: Making Design Reuse Work

Webinar: Making Design Reuse Work
by Daniel Nenni on 04-26-2014 at 9:00 pm

Please join me for an IP conversation in collaboration with ClioSoft on Wednesday, April 30th, 2014 @ 11:00 AM PST. At the EDPS Workshop IP day there were two interesting presentations on IP reuse. The first one was by Warren Savage of IPextreme: Top Ten Reasons Why Internal IP Reuse Fails. The second was by Ranjit Adhikary of ClioSoft:… Read More


Digital, Analog, Software, IP – Isn’t it all just the same?

Digital, Analog, Software, IP – Isn’t it all just the same?
by Daniel Payne on 04-25-2014 at 8:31 pm

Designing an SoC requires a team, and the engineers typically use lots of specialized EDA software and semiconductor IP to get the job done. Many have started to ask about how designing a chip is different than designing and managing a large software project, or how is analog design different than digital design in terms of managing… Read More


Welcome, LPDDR4!

Welcome, LPDDR4!
by Eric Esteve on 04-23-2014 at 3:46 am

Thanks to memory controller expert Marc Greenberg, Marketing Director for DDRn Controller IP with Synopsys, for this post “Qualcomm announces first application processor with LPDDR4 capability”. According with Marc, this Application Processor, the Snapdragon 810, is “the first product that I’m aware of that will use LPDDR4… Read More


Learning an HDL Simulator

Learning an HDL Simulator
by Daniel Payne on 04-23-2014 at 1:52 am

Learning an HDL language or an HDL simulator are two different things, so I wanted to see what was available for learning a vendor-specific HDL simulator. I’ve already taught Verilog as an instructor using both ModelSim and Active-HDL simulators, however we only used a handful of commands in the class and labs in order to … Read More


You didn’t say it has to work

You didn’t say it has to work
by Don Dingee on 04-22-2014 at 8:00 pm

“Failure to plan is planning to fail.” If that is true – and it has been quoted verbatim or slightly modified so many times throughout modern history, there has to be some truth – why does most of the engineering community seem to detest planning so much?

Engineering planning doesn’t mean whipping out a block diagram or pseudo code,… Read More


Importance of Data Management in SoC Verification

Importance of Data Management in SoC Verification
by Pawan Fangaria on 04-22-2014 at 6:00 am

In an era of SoCs with millions of gates, hundreds of IPs and multiple ways to verify designs through several stages of transformations at different levels of hierarchies, it is increasingly difficult to handle such large data in a consistent and efficient way. The hardware and software, and their interactions, have to be consistent… Read More


Ten Innovative Debugging Techniques – Pre & Post Layout

Ten Innovative Debugging Techniques – Pre & Post Layout
by Pawan Fangaria on 04-21-2014 at 8:00 pm

In a complex world of SoCs with multi-million gates and IPs from several heterogeneous sources, verification of a complete semiconductor design has become extremely difficult, and it’s not enough. In order to ascertain the right intent of the design throughout the design cycle, debugging at various stages of the design cycle… Read More