I talked to Mark Milligan this morning, who has just joined Calypto as VP Marketing. I first met Mark back when he was at CoWare and I was at VaST or maybe it was Virtutech. Then he moved on and ran marketing at SpringSoft which, I’m sure you remember, Synopsys acquired. I asked him what encouraged him to join Calypto.
He said that there is a lot of technology that has been brewing for years. When Mark was at the Open SystemC Initiative (OSCI) he said that synthesis from C was the holy grail. But back then the technology was immature. The other big problem was that there wasn’t a very good verification flow. Having simulated everything at the C (or SystemC) level it all had to be resimulated at RTL to make sure that the high level synthesis had done its job.
Four things have changed in the intervening years:
- High level synthesis technology in Catapult has got really good
- The sequential equivalence checking (SLEC) technology that Calypto originally developed has got to be good, so that now there is a formal verification flow
- Power has become the dominant constraint in algorithmic design, and in the FinFET era dynamic power in particular
- The complexity of the designs that people are doing using this technology is mind-boggling
The approach is not applicable to every type of IP, often there is legacy RTL or that RTL is simply the right level to do the design. But modems often have changing specifications, graphics is always about improving the algorithms. By being able to simulate the design at the C or SystemC level there is a huge gain in performance. But the biggest thing driving adoption is that there is serious pain in some of these areas and an RTL-based approach doesn’t work. It is simply not possible to iterate designs fast enough, to move them from one process generation to the next and so on.
At DAC, Calypto have customer presentations on how companies are using the products to do these types of design. Calypto have 3 products. The Catapult high-level synthesis (that came from Mentor originally). The sequential logical equivalence checking (SLEC). And the PowerPro sequential power reduction technology. Catapult and PowerPro allow design to be done at high-level and SLEC gives a corresponding verification flow.
But the big coup is that Google will be presenting how they use Catapult for design of video processors, that they call VP9. By doing it at the C level they can share code with partners in a quasi-open-source way. Their partners can also feed improvements back to Google. Further, by moving up to the C level it is much easier for “software types” to do hardware design. It is all about being able to take the algorithm and efficiently implement it in silicon (either and FPGA or gates or even just run it on a processor) and meet the power budget.
Calypto’s DAC booth is #2333.
More articles by Paul McLellan…