Coventor just rolled out the latest version of SEMulator3D, their virtual fabrication tool. Very conveniently it is SEMICON West this week and they have a booth. I dropped by and got a demo from David Fried, Coventor’s CTO about all the new stuff. He’s very proud of SEMulator3D’s new logo but mostly he is proud… Read More
Electronic Design Automation
How Emulation Enables Complex Power Intent Modeling
As the number of CPU, GPU, and IP is growing in an SoC, power management is becoming more and more a complex task in itself. A single tool or methodology may not be enough for complete power management and verification of an SoC. In an SoC, there can be multiple modes of operations involving hardware and software interactions, different… Read More
Benefits of RTL Power Budgeting
Only one company at the recent DAC conference and exhibit had a set of four interacting disciplines: Fluids, Structures, Electronics and Systems. Did you guess that the company was ANSYS? I get so IC focused at times that I almost forget that chips plug into boards, that boards become systems, and that systems drive and control mechanical… Read More
Improve RTL Physically for Design Quality & Convergence
The SoC design teams are usually divided between front-end and back-end specialties. It is neither practical nor advisable to combine the two teams in order to better tackle the back-end issues upfront during the front-end design. However, a common problem is that the issues at the layout stage have very little scope for resolution… Read More
Conquering the Next IoT Challenges with FPGA-Based Prototyping
The need for ever-connected devices is skyrocketing. As I fiddle with my myriad of electronic devices that seem to power my life, I usually end up wishing that all of them could be interconnected and controlled through the Internet. The truth is, only a handful of my devices are able to fulfill that wish, but the need is there and developers… Read More
Which High B/W Memory to Select after DDR4?
Once upon a time, RAM technology was the driver of the semiconductor process. DRAM products were the first to be designed on a newest technology node and DRAM was used as a process driver. It was 30 years ago and the most aggressive process nodes were ranging between 1um and 1.5 um (1 500 nm!). Then in the 1990 the Synchronous Dynamic … Read More
Tackling Layout Gradient Effects in 16 nm FinFET using Layout Automation
My first exposure to automating IC layout was back in the 1980’s at Intel where I coded a layout compiler to auto-generate about 6% of a graphics processor chip. The need to use automation for IC layout continues today, and with the advent of FinFET technology there are some new challenges like layout gradient effects that … Read More
Updates for Effective Collaboration
Managing any design data management system requires a policy on how often users should be submitting their changes to the central repository. If users commit frequently with less local testing then other users will more likely see errors. If commits are done less often, but with better testing, then other users are protected from… Read More
Power Management Gets Tricky in IP Driven World
Today, an SoC can have multiple instances of an IP and also instances of many different IPs from different vendors. Every instance of an IP can work in a separate mode and requires a dedicated power arrangement which may only be formalized at the implementation stage. The power intent, if specified earlier, will need to be re-generated… Read More
Circuit Simulation Update from #52DAC
Actual users of circuit simulators told their design and simulation stories at DAC during a luncheon sponsored by Synopsys on June 8th. I always prefer to hear from a design engineer versus a marketing person about what tool they use for circuit simulation, and how it helps them analyze their design goals. This year there were engineers… Read More


Silicon Insurance: Why eFPGA is Cheaper Than a Respin — and Why It Matters in the Intel 18A Era