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EDA

Electronic Design Automation

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Physically Aware DFT Improves PPA

Physically Aware DFT Improves PPA
by Pawan Fangaria on 02-16-2015 at 7:00 pm
Categories: Cadence, EDA

Introducing on-chip test circuitry has become a necessary criteria for an ASIC’s post manufacture testability. The test circuitry is usually referred as DFT (Design-for-Test) circuit. A typical methodology for introducing DFT circuit in a design is to replace usual flip-flops with special types of flip-flops called ‘scan… Read More

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Secure Processor for IoT

Secure Processor for IoT
by barun on 02-16-2015 at 1:00 pm
Categories: EDA, IoT

In my last blog “Processor for IoT” I have discussed security as one of the key requirements for processor used in IoT devices. In this blog we will analyze different method of hacking and some techniques which can be used to prevent those security breaches.

One of the common ways of attack is to probe address and data … Read More

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Do You Need a Silicon Catalyst?

Do You Need a Silicon Catalyst?
by Daniel Nenni on 02-14-2015 at 7:00 pm
Categories: EDA, Foundries, IP, Synopsys, TSMC

Lately there has been significant concern over the rising costs of designing in silicon and the troubling decline in venture investments in semiconductors. These alarming trends include fewer IPOs, a falloff in the amount and frequency of early stage seed investments, and comparatively low industry organic growth rates. A … Read More

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More Test Points are Better

More Test Points are Better
by Daniel Payne on 02-14-2015 at 7:00 am
Categories: EDA

I got really involved in testability back at CrossCheck in the 1990’s when they designed a way for Gate Arrays to have 100% observability without any Design For Test (DFT) requirements on designers. The Japanese Gate Array companies loved this approach and their customers enjoyed the highest test coverage without being… Read More

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A Comprehensive Automated Assertion Based Verification

A Comprehensive Automated Assertion Based Verification
by Pawan Fangaria on 02-13-2015 at 4:00 pm
Categories: EDA

Using an assertion is a sure shot method to detect an error at its source, which may be buried deep within a design. It does not depend on a test bench or checker, and can fire automatically as soon as a violation occurs. However, writing assertions manually is very difficult and time consuming. To do so require deep design and coding… Read More

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Dealing with FPGA IP in all its forms

Dealing with FPGA IP in all its forms
by Don Dingee on 02-12-2015 at 10:00 pm
Categories: EDA, FPGA, Synopsys

One of the recurring themes I see here in the pages of SemiWiki and elsewhere is this pitched, bordering on religious battle between Altera and Xilinx. Just because both are FPGA technologies, the tendency is to put them in the same bucket, drawing direct comparisons between them. Some folks say there is no comparison; Xilinx has… Read More

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ADAS Going Mainstream One Chip at a Time

ADAS Going Mainstream One Chip at a Time
by Majeed Ahmad on 02-12-2015 at 1:00 pm
Categories: EDA, IoT, STMicroelectronics

Advanced Driving Assistance Systems (ADAS) are an essential element in the vision of autonomous or semi-autonomous vehicles, and they are becoming available today. The ADAS automotive technology raises driving safety by detecting obstacles around the vehicle such as other vehicles and pedestrians, as well as traffic signs… Read More

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How Well is HSPICE Tracking Current Design Trends?

How Well is HSPICE Tracking Current Design Trends?
by Tom Simon on 02-11-2015 at 10:00 pm
Categories: EDA, Synopsys

For about 5 years now Synopsys has held an HSPICE SIG event in conjunction with DesignCon. It features a small vendor faire with companies that partner with Synopsys on HSPICE flows. They also have a dinner with industry/customer speakers and provide an update on HSPICE development. Lastly there is a Q&A where customers get… Read More

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UVM Debugging Made Easy & Productive in Questa

UVM Debugging Made Easy & Productive in Questa
by Pawan Fangaria on 02-11-2015 at 2:00 pm
Categories: EDA

As design complexity and size is increasing, SoC verification has become one of the most difficult and time consuming tasks in the design closure.UVM (Universal Verification Methodology, an accellera initiative) is one of the best verification methodologies that support common language, coherent strategy, clarity and transparency… Read More

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Chips Are Going 3D, DRC Needs to Go 3D Too

Chips Are Going 3D, DRC Needs to Go 3D Too
by Paul McLellan on 02-10-2015 at 7:00 am
Categories: Coventor, EDA

The last paradigm shift in DRC was around 0.35um when designs got too large to handle as flat data, and hierarchical approaches were required. Back then the design rules themselves were not that complex, the explosion of data volume came from the complexity of the design itself. But each process node added more design rules intricacies… Read More