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Electronic Design Automation
Last week at #54DAC there was a talk by Michael Yu from the CAD group of Oracle who discussed how they designed their latest generation of SPARC chips, with an emphasis on the reliability simulations. The three features of the latest SPARC family of chips are:
Right before #54DAC I participated in a webinar with Methodics on “New Concepts in Semiconductor IP Lifecycle Management” with Simon Butler, CEO of Methodics, Michael Munsey, Vice President of Business Development and Strategic Accounts, and Vishal Moondhra, Vice President of Applications. Thewebinar introduced… Read More
The Siemens purchase of Mentor last year for a premium $4.5B was a bit of a shock to me as I have stated before. I had an inkling a Mentor acquisition was coming but Siemens was not on my list of suitors. The reviews have been mixed and the Siemens commitment to the IC EDA market has been questioned so I spent some time on this at #54DAC.
First… Read More
It takes courage and perhaps even a little insanity to start a new EDA venture these days – unless you have a decently differentiated value proposition in a hot market. One company that caught my eye, Austemper, seems to measure up to these standards (though I can’t speak to the insanity part). They offer EDA tooling specifically… Read More
Synopsys PrimeTime PX, popularly known as PT-PX, is widely recognized as the gold standard for power signoff. Calculation is based on a final gate-level netlist reflecting final gate selections and either approximate interconnect parasitics or final parasitics based on the post-layout netlist. The only way to get more accurate… Read More
It is self-evident that large systems of any type would not be possible without hierarchical design. Decomposing a large system objective into subsystems, and subsystems of subsystems, has multiple benefits. Smaller subsystems can be more easily understood and better tested when built, robust 3[SUP]rd[/SUP] party alternatives… Read More
DAC is coming, next week, in beautiful downtown Austin at the Convention Center. I’ll be there Monday and Tuesday, running around the exhibit area. If you haven’t yet got your plane and hotel tickets, drop everything and start looking. I’m guessing this will be as popular as it always is, especially given the venue. I know of multiple… Read More
With the premier conference for semiconductor design enablement just around the corner I would like to take this time and space to talk about what is really happening at the #54DAC and that would be the parties! Granted the DAC parties are nothing like we used to have in the 1980s and the 1990s since we have matured as an industry but … Read More
Webinars are a powerful way for engineers to get updated on EDA and IC design approaches, so I’m sharing what I viewed last month at a Silvaco webinar on TFT and FPD design. You probably are using a TFT LCD display in your TV, monitor, mobile phone, video game system, GPS device or projector. The custom IC design flow offered by… Read More
While some might have expected the exponential growth in design rules number and complexity to cool down a little, it looks as if these are only heating up more. The multiplicity of technology nodes, lithography options, , fundamental technology options (Bulk, FD-SOI, FinFET), different process flavors and specific applications,… Read More
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Solving the EDA tool fragmentation crisis