Having the right tool for the job at hand is always a joy, and when your IC project involves RTL code, gates, transistors and even parasitic interconnect, then you need some EDA tool help for debugging and finding out why your design behaves the way it is. An FAE named Sujit Roy did a conference call with me last week to show what StarVision… Read More
Electronic Design Automation
SpyGlass Gets its VC
It’s a matter of pride to me and many others from Atrenta days that the brand we built in SpyGlass has been so enduring. It seems that pretty much anyone who thinks of static RTL checking thinks SpyGlass. Even after Synopsys acquired Atrenta, they kept the name as-is, I’m sure because the brand recognition was so valuable.
Even good… Read More
Security in I/O Interconnects
I got a chance to chat with Richard Solomon at Synopsys recently about a very real threat for all of us and what Synopsys is doing about it. No, the topic isn’t the Coronavirus, it’s one that has been around a lot longer and will continue to be a very real threat – data and interconnect security.
First, a bit about Richard. He is the technical… Read More
Prevent and Eliminate IR Drop and Power Integrity Issues Using RedHawk Analysis Fusion
I had the opportunity to preview an upcoming SemiWiki webinar on IR drop and power integrity. These topics, all by themselves, have real stopping power. Almost everyone I speak with has a story to tell about these issues in a recent chip design project. When you combine hot topics like this with a presentation that details the collaboration… Read More
Mentor Masterclass on ML SoC Design
I was scheduled to attend the Mentor tutorial at DVCon this year. Then coronavirus hit, two big sponsors dropped out and the schedule was shortened to three days. Mentor’s tutorial had to be moved to Wednesday and, as luck would have it, I already had commitments on that day. Mentor kindly sent me the slides and audio from the meeting… Read More
Cadence Digital Full Flow Optimized to Deliver Improved Quality of Results with Up to 3X Faster Throughput
Artificial intelligence (AI) and machine learning (ML) are hot topics. Beyond the impact these technologies are having on the world around us, they are also having impact on the semiconductor and EDA ecosystem. I posted a blog last week that discussed how Cadence views AI/ML, both from a tool and ecosystem perspective. The is one… Read More
A Conversation with Wally Rhines: Predicting Semiconductor Business Trends After Moore’s Law
Wally Rhines is one of the most prolific speakers the semiconductor industry has ever experienced. Wally is also one of the most read bloggers on SemiWiki.com, sharing his life’s story which is captured in his first book: From Wild West to Modern Life the Semiconductor Evolution.
On April 2nd at 10am PDT we will host Wally on a live… Read More
Machine Learning for EDA – Inside, Outside and Everywhere Else
Artificial intelligence (AI) is everywhere. The rise of the machines is upon us in case you haven’t noticed. Machine learning (ML) and its associated inference abilities promise to revolutionize everything from driving your car to making breakfast. We hear a lot about the macro, end-product impact of this technology, but there… Read More
Webinar on Tools and Solutions for Analog IP Migration
The commonly advanced reason for IP reuse is lower cost and shorter development time. However, IP reuse presents its own challenges, especially for analog designs. In the case of digital designs, once a new standard cell library is available, it is usually not too hard to resynthesize RTL to create new working silicon. For analog… Read More
Innovation in Verification March 2020
This blog is the next in a series in which Paul Cunningham (GM of the Verification Group at Cadence), Jim Hogan and I pick a paper on a novel idea we appreciated and suggest opportunities to further build on that idea.
We welcome comments on our blogs and suggestions for new topics if they’re based on published work.
The Innovation
Our… Read More
Basilisk at Hot Chips 2025 Presented Ominous Challenge to IP/EDA Status Quo