SILVACO 073125 Webinar 800x100
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White Paper – Mixed Signal Verification for Nanometer SOCs

White Paper – Mixed Signal Verification for Nanometer SOCs
by Tom Simon on 08-19-2020 at 10:00 am

Mixed signal SOCs

The number of touchpoints between analog and digital circuits in high performance SoCs is increasing. This is not a problem because it is possible to implement critical analog blocks directly on nanometer scale digital ICs. However, in many cases digital interfaces or digital feedback circuitry configures these analog blocks… Read More


CEO Interview: Anna Fontanelli of Monozukuri

CEO Interview: Anna Fontanelli of Monozukuri
by Daniel Nenni on 08-19-2020 at 6:00 am

ANNA

Anna has more than 25 years of expertise in managing complex R&D organizations and programs, giving birth to a number of innovative EDA technologies. She has pioneered the study and development of several generations of IC and package co-design environments and has held senior positions at leading semiconductor and EDA … Read More


The Big Three Weigh in on Emulation Best Practices

The Big Three Weigh in on Emulation Best Practices
by Mike Gianfagna on 08-18-2020 at 10:00 am

Emulation Best Practices

As software content increases in system-on-chip and system-in-package designs, emulation has become a critical enabling technology for the software team. This technology offers software developers the opportunity to verify their code in against a high-fidelity model of the target system that actually executes fast enough… Read More


CEO Interview: Isabelle Geday of Magillem

CEO Interview: Isabelle Geday of Magillem
by Daniel Nenni on 08-14-2020 at 6:00 am

isabelle geday

Isabelle Geday is the Founder and CEO of Magillem Design Services, headquartered in Paris, France. Isabelle has over 40 years of experience creating innovative platform solutions, in various industries such as oil, telecommunications, IT and EDA. She has a proven track record in managing startup companies internationally,… Read More


Cadence Increases Verification Efficiency up to 5X with Xcelium ML

Cadence Increases Verification Efficiency up to 5X with Xcelium ML
by Mike Gianfagna on 08-13-2020 at 6:00 am

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SoC verification has always been an interesting topic for me. Having worked at companies like Zycad that offered hardware accelerators for logic and fault simulation, the concept of reducing the time needed to verify a complex SoC has occupied a lot of my thoughts. The bar we always tried to clear was actually simple to articulate… Read More


RISC-V SDKs, from IP Vendor or a Third Party?

RISC-V SDKs, from IP Vendor or a Third Party?
by Bernard Murphy on 08-12-2020 at 6:00 am

RISC V min

Like many of us, I’m a fan of open-source solutions. They provide common platforms for common product evolution, avoiding a lot of unnecessary wheel re-invention, over and over again. Linux, TensorFlow, Apache projects, etc., etc. More recently the theme moved into hardware with OpenCores and now the RISC-V ISA. All good stuff.… Read More


HCL Webinar Series – HCL VersionVault Delivers Version Control and More

HCL Webinar Series – HCL VersionVault Delivers Version Control and More
by Mike Gianfagna on 08-06-2020 at 10:00 am

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HCL is an interesting organization. You may know them as an Indian company that provides software and hardware services.  At about $10B US and over 110,000 employees working around the world, they are indeed a force in the industry. They’ve also created a software company called HCL Software that develops tools and technologies… Read More


Structural CDC Analysis Signoff? Think Again.

Structural CDC Analysis Signoff? Think Again.
by Bernard Murphy on 08-05-2020 at 6:00 am

strainer min

Talking not so long ago to a friend from my Atrenta days, I learned that the great majority of design teams still run purely structural CDC analysis. You should sure asynchronous clock domains are suitably represented in the SDC, find all places where data crosses between those domains that require a synchronizer, gray-coded FIFO… Read More


Cadence on Automotive Safety: Without Security, There is no Safety

Cadence on Automotive Safety: Without Security, There is no Safety
by Mike Gianfagna on 08-04-2020 at 10:00 am

Attack vectors and EDA countermeasures

One of the Designer Track at this year’s DAC focused on the popular topic of automotive electronics.  The title was particularly on-point, The Modern Automobile: A Safety and Security “Hot Zone”. The session was chaired by Debdeep Mukhopadhyay, a Professor at the Indian Institute of Technology in Kharagpur.

This special, invited… Read More


Webinar Replay – Designing and Verifying HBM ESD Protection Networks

Webinar Replay – Designing and Verifying HBM ESD Protection Networks
by Tom Simon on 08-03-2020 at 10:00 am

Promo Ad 400x400 2

Every chip needs ESD protection, especially RF, analog and nm designs. Because each type of design has specific needs relating to IOs, pad rings, operating voltage, process, etc. it is important that the ESD protection network is carefully tailored to the design. Also because of interactions between the design and its ESD protection… Read More