Vision pipelines, from image signal processing (ISP) through AI processing and fancy effects (super-resolution, Bokeh and others) has become fundamental to almost every aspect of the modern world. In automotive safety, robotics, drones, mobile applications and AR/VR, what we now consider essential we couldn’t do without… Read More
Agile and Verification, Validation. Innovation in Verification
Agile methods in hardware design are becoming topical again. What does this mean for verification? Paul Cunningham (GM, Verification at Cadence) and I continue our series on research ideas. We’re also honored this month to welcome Raúl Camposano to our blog as a very distinguished replacement for Jim Hogan. As always, feedback… Read More
Cadence Dynamic Duo Upgrade Debuts
Cadence calls their hardware acceleration platforms, Palladium Z2 for fast pre-silicon hardware debug and Protium X2 for fast pre-silicon software validation, their Dynamic Duo. With good reason. Hardware acceleration is now fundamental to managing the complexity of verification and validation for large systems, hardware… Read More
Reducing Compile Time in Emulation. Innovation in Verification
Is there a way to reduce cycle time in mapping large SoCs to an FPGA-based emulator? Paul Cunningham (GM, Verification at Cadence), Jim Hogan (RIP) and I continue our series on research ideas. As always, feedback welcome.
The Innovation
This month’s pick is Improving FPGA-Based Logic Emulation Systems through Machine Learning… Read More
Cadence Underlines Verification Throughput at DVCon
Paul Cunningham, CVP and GM of the System Verification Group at Cadence gave the afternoon Keynote on Tuesday at DVCon and doubled down on his verification-throughput message. At the end of the day, what matters most to us in verification is the number of bugs found and fixed per dollar per day. You can’t really argue with that message.… Read More
TECHTALK: Hierarchical PI Analysis of Large Designs with Voltus Solution
Power integrity analysis in large chip designs is especially challenging thanks to the huge dynamic range the analysis must span. At one end, EM estimation and IR drop through interconnect and advanced transistor structures require circuit-level insight—very fine-grained insight but across a huge design. At the other, activity… Read More
Finding Large Coverage Holes. Innovation in Verification
Is it possible to find and prioritize holes in coverage through AI-based analytics on coverage data? Paul Cunningham (GM, Verification at Cadence), Jim Hogan and I continue our series on research ideas. As always, feedback welcome.
The Innovation
This month’s pick is Using Machine Learning Clustering To Find Large Coverage … Read More
2020 Retrospective. Innovation in Verification
Paul Cunningham (GM, Verification at Cadence), Jim Hogan and I launched our series on Innovation in Verification at the beginning of last year. We wanted to explore basic innovations and new directions researchers are taking for hardware and system verification. Even we were surprised to find how rich a seam we had tapped. We plan… Read More
ML plus formal for analog. Innovation in Verification
Can machine learning be combined with formal to find rare failures in analog designs? ML plus formal for analog – neat! Paul Cunningham (GM, Verification at Cadence), Jim Hogan and I continue our series on research ideas. Here an idea from analog simulation sampling. Feel free to comment.
The Innovation
This month’s pick… Read More
Cadence is Making Floorplanning Easier by Changing the Rules
SoC designs are getting more complex, resulting in a higher level of difficulty to get anything done. This trend is well-known. What I want to focus on here is how to deal with the issue of complexity. There are many approaches to taming this problem — faster algorithms for one, and improved algorithm efficiency or the ability to run… Read More