When I was reading the recent Daniel Payne article “Designing Change Into Semiconductor Techonomics” with commentary on a recent presentation from Aart de Geus of Synopsys, one chart jumped out at me: the most popular process node for new design starts today is 180nm.
Upon mentioning that to a few of my IoT counterparts, they quickly dismissed it as an insignificant point. Any meaningful new design is on an advanced node, right? Dead wrong, as it turns out. Mixed signal designs and microcontrollers thrive on older nodes, and the 180nm observation points to one particular process.
Sometimes, press releases assume way too much – balance is needed between overdefining common terms and boring a reader with history, and omitting a mention of an important point that may establish why a new release is significant. Such is the case with the recent Sidense news, qualifying their 1T-OTP NVM macros in TSMC’s 180nm BCD 1.8/5.0V Gen 2 process.
I’m an applications guy, not a process guy, and I’m not as close as some of my SemiWiki counterparts to TSMC, so frankly I had to go figure out what this means in the bigger picture. On the surface, we know Sidense is touring the world presenting at various stops on the TSMC Technology Symposium, so news of a TSMC process qualification is timely. But, why this one?
Aart’s chart was also fresh in my mind, so I was primed to take a closer look at what designs are still going on at 180nm. The answer is analog and power management electronics, in many cases with a microcontroller core in the mix to provide localized control and communication such as CAN or LIN for automotive applications.
BCD stands for “bipolar-CMOS-DMOS”, combining three transistor types and voltages into a single mixed signal substrate. ST claims to have invented BCD technology, and obviously others have run with it, including TSMC. The evolution of TSMC 180nm BCD continued in June 2012, when they teamed with Analog Devices on a Gen 2 enhancement with significant benefits:
Performance enhancements achieved with the 0.18 micron, 5-volt process include an order of magnitude noise improvement, a 70 percent lower standby leakage current, a 50 percent improvement in linearity and a 50 percent better capacitor and resistor matching.
Now, the motivation is a lot clearer. Sidense mentioned it took a while for them to achieve Gen 1 qualification in April 2013. By then, new design starts were probably already moving to Gen 2 to capture the above benefits, particularly the 10x noise improvement and a dramatic reduction in leakage current. With the essential requirement of analog trimming, and the usefulness of 1T-OTP NVM in implementing it, the Sidense availability on Gen 2 is welcome news for customers.
The TSMC 180nm BCD Gen 2 process targets high temperature, high reliability automotive applications, thus there is a relatively long qualification cycle. AEC-Q100 Grade 0 carries a temperature rating of -40C to 150C, suitable for “under the hood”. For automotive, data retention targets are over 10 years, so an accelerated requirement of 2000 hours at 150C has to be demonstrated.
As Analog Devices pointed out, they have worked with TSMC on BCD processes at 600nm, 350nm, and 180nm, and Dialog Semiconductor is entering the fray on 130nm – over time, the sweet spot for design starts in Aart’s presentation will likely move down to 130nm. Digital gets a lot of the attention, but it is an analog world, and mature nodes for mixed signal will play a big part for a very long time.