DesignCon is a unique conference — its tagline is “Where the Chip meets the Board”. Held each January in Santa Clara, the conference showcases a wealth of new technologies for advanced packaging, printed circuit board fabrication, connectors, cables, and related analysis equipment (e.g, BERT, VNA, scopes). Of specific… Read More
Author: Tom Dillinger
DesignCon 2016 — signal integrity must be power-aware!
The “Era of the Photon” is here!
The 50 year anniversary of the publication of Moore’s Law was recently celebrated, highlighting the tremendous advances in the Microelectronics Eraof the period in human history known as the Information Age. However, the technical and economic challenges currently faced by the microelectronics industry are bringing into… Read More
A Synergistic Chip-Package-System Analysis Methodology
Looking back, 2015 was a significant year for mergers and acquisitions in the EDA industry. The Semiwiki team maintains a chronology of major transactions here.
As I was reviewing this compendium, one of the entries that stands out is the acquisition of Apache Design Solutions by Ansys, Inc. a couple of years ago.
At that time, there… Read More
A (R)evolution in Hardware-based Simulation Acceleration
The most exciting products in our industry are those that are both evolutionary and revolutionary. Cadence has just announced an update to their hardware simulation acceleration platform – Palladium Z1 – which continues the evolution of the unique capabilities of processor-based acceleration, plus a revolutionary approach… Read More
FinFET Reliability Analysis with Device Self-Heating
At the recent TSMC OIP symposium, a collaborative presentation by Synopsys and Xilinx highlighted the importance of incorporating the local FinFET device self-heating temperature increase on the acceleration of device reliability mechanisms.… Read More
Extendible Processor Architectures for IoT Applications
The Internet of Things has become a ubiquitous term, to refer to a broad (and somewhat ill-defined) set of electronic products and potential applications – e.g., wearables, household appliances and controllers, medical applications, retail applications (signage, RFID), industrial automation, machine-to-machine communication,… Read More
Wafer-Level Chip-Scale Packaging Technology Challenges and Solutions
At the recent TSMC OIP symposium, Bill Acito from Cadence and Chin-her Chien from TSMC provided an insightful presentation on their recent collaboration, to support TSMC’s Integrated FanOut (InFO) packaging solution. The chip and package implementation environments remain quite separate. The issues uncovered in bridging… Read More
Optimizing Quality-of-Service in a Network-on-Chip Architecture
The Linley Group is well-known for their esteemed Microprocessor Report publication, now in its 28th year. Accompanying their repertoire of industry reports, TLG also sponsors regular conferences, highlighting the latest developments in processor architecture and implementation.
One of the highlights of the conference… Read More
Meeting DFM Challenges with Hierarchical Fill Data Insertion
To describe the latest methodology for the addition of Design for Manufacturability fill shapes to design layout data, it’s appropriate to borrow a song title from Bob Dylan – The Times They Are A Changin’. The new technical requirements are best summarized as: “The goal is now to add as much fill as possible, which (ideally) looks… Read More
A FinFET BSIM-CMG model update from UC-Berkeley
Every designer relies upon an underlying “compact” device model for circuit simulations – these models are the lifeblood of the IC industry. Designers may not be aware that there is an organization that qualifies models – the Compact Model Coalition – which operates under the umbrella of the Si2 Consortium: http://www.si2.org/cmc_index.php… Read More
The Data Crisis is Unfolding – Are We Ready?