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Four Takeaways from the TSMC OIP 2015

Four Takeaways from the TSMC OIP 2015
by Tom Dillinger on 09-20-2015 at 2:30 am

Paul M. did an excellent job summarizing the technical information that TSMC presented at the recent Open Innovation Platform symposium. I’d like to also share an impression on four areas that struck me as key to TSMC’s strategy.

(1) process evolution: HP/LP, then ULP

TSMC’s early node adopters represent the high-performance and mobile computing markets, and are primarily focused on PPA scaling. These customers drive initial HP/LP process development and IP qualification.

There has been an “Ultra-Low Power” variant developed – both 40ULP and 28ULP will be in risk production soon.

The N16FFC process offering announced earlier this year (risk production mid-2016) is both a cost-driven process enhancement, as well as a ULP variant. A wide range of operating environments is expected, to address automotive and IoT market opportunities. The salient features include:

  • an additional Extra-High Vt device (SVT, LVT, HVT, and EHVT)
  • additional process controls to manage variation
  • PDK model accuracy is key for VDD = 0.55–0.8V (lower for ULP)
  • IP needs to be qualified over 0.55-0.8V (lower for ULP)

Cliff Hou at TSMC showed device model and circuit characterization data down to 0.4V for N16FFC-ULP. Circuit robustness and delay variation analysis will be a key requirement at these low operating voltages. Cliff indicated users will be applying “don’t use” overrides for some cells at very low VDD.

Additionally, for N16FFC-ULP, statistical variation distributions will be non-Gaussian – a review of “high-sigma” circuit analysis methods may be needed, as well.

NET: TSMC anticipates the cost- and power-driven IoT market will migrate to N16FFC-ULP. (Many have conjectured these designs would remain in older nodes indefinitely.) This will require significant R&D investment in process development, modeling, and circuit design + qualification.

(2) early engagement is becoming even earlier

Cliff highlighted that the PDK development timeline has changed, both for IP developers and early adopters. Traditionally, PDK v0.5 and v1.0 releases were the major milestones:

  • v0.5 PDK – TSMC foundation IP release, EDA reference flow certification
  • v1.0 PDK – 3rd Party IP release, new product tapeouts

The new IP collaboration model for N10FF pulls the PDK v0.5 milestones back to PDK v0.1/v0.2.

NET: To maintain a very aggressive “Moore’s Law” process development timeline for N10 and N7, EDA developers and IP providers must collaborate on new tool features earlier, and must be able to adapt quickly as process development evolves from PDK v0.1 to v1.0 risk production.

(3) embedded memory development is (still) key

TSMC highlighted the R&D investment in embedded non-volatile memory – their embedded Flash offering will be extended to 40nm and 28nm soon. Yet, concerns about scaling and retention have driven researchers to look for (non-electron storage based) alternatives.

TSMC also highlighted the opportunities for potential replacements for eFLASH.

TSMC has a long history of advanced research in Spin Transfer Torque magnetic RAM, aka STT-MRAM (e.g., a joint paper with Qualcomm at IEDM-2009). Additionally, they highlighted recent progress in R&D work on embedded Resistive RAM (ReRAM) technology.

NET: Look for 2017 to be a “watershed” year for embedded non-volatile IP, to be introduced in advanced process nodes.

(4) TSMC is focused on advanced multi-die packaging technology

The 2.5D CoWoS offering has been in production for a couple of years, as exemplified by the multi-FPGA design from Xilinx – that technology has been extended to larger substrates using multiple field exposures (“CoWoS-XL”).

The newer Integrated FanOut (InFO) chip-scale packaging technology will be available for risk production later this year. It supports package-on-package (PoP) and 3D stacked die assembly options, similar to existing offerings. A cost and size reduction is achieved using wiring planes and through vias embedded in the package molding compound.

EDA vendors have developed the physical implementation and electrical analysis chip-package co-design flows for this technology – more in a subsequent blog.

NET: TSMC is evolving into much more than just a wafer foundry, establishing their support for 2.5D/3D packaging. This is a both a technical and business strategy, to address the growing markets requiring 3D packaging, taking on more of an OSAT role.


Also read: TSMC OIP: What to Do With 20,000 Wafers Per Day

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