Most of the buzz on network-on-chip is around simplifying and scaling interconnect, especially in multicore SoCs where AMBA buses and crossbars run into issues as more and more cores enter a design. Designers may want to explore how NoCs can help with a more power-aware approach.… Read More
Author: Don Dingee
Thread is why Nest has extra 802.15.4 goodies
From last week: “Chipmakers can’t afford to wait on the sidelines, hoping their standard fare gets picked up and fits in with one of these [#IoT]teams.” This week, it’s ARM, Freescale, and Silicon Labs joining with Google and others on Thread. Yet another consortium? A lot more to this story.… Read More
Chip side of the Open Interconnect Consortium
Maybe it’s my competitive analysis gene, or too many years spent hanging out with consortium types, but I’m always both curious and skeptical when a new consortium arises – especially in a crowded field of interest. The dynamics of who aligns with a new initiative, and how they plan to go to market compared to other entities, prompts… Read More
Fantasy Tech-Ball and the Intel Rumor Wire
Reading Intel analysis lately has been a lot like reading fantasy baseball analysis. Intel should buy Altera. Intel should waive Atom. Intel should fab for Apple. All of those have a near-zero probability of happening IMHO, and yet pundits continue to pitch their version of alternate reality, dealing away product lines and strategies… Read More
A song of optimization and reuse
If you hang around engineers for any time at all, the word optimization is bound to come up. The very definition of engineer is to contrive or devise a solution. With that anointing, most engineers are beholden to the idea that their job is creating, synthesizing, and perfecting a solution specifically for the needs of a unique situation.… Read More
I’ll be with you in a second
One aspect of always-on is power conservation, being able to respond to events without having a device constantly in full-power mode. This month, the announcement of the Amazon Fire Phone and details revealed about the Google Android Wear SDK suggest another important dimension: the competitive advantage of rapid, frictionless… Read More
Real FPGAs don’t eat fake test vectors
Vector blasting hardware is as old as digital test methodology itself. In the days of relatively simple combinational and finite state machine logic, a set of vectors aimed broadside at inputs could shake loose most faults with observable outputs. With FPGAs, creating an effective set of artificial test vectors has become a lot… Read More
On the Road from Makers to Consumers
It’s time to break with conventional thinking. For decades, the measure of success for semiconductors has been OEM design wins. Most consumers haven’t known, or cared, about what is inside their electronic gadgets, as long as they work. That may be about to change, because a new intermediary is finding its voice – and being… Read More
Non-separation of power and performance
How much power does a system consume? The simplistic path to power estimation for a system used to be tossing a few metrics – standby, typical, worst case, with figures pulled from a datasheet, simulation, or physical measurement – into a spreadsheet. After filling the remaining holes with SWAG (scientific wild-ass guesses), … Read More
Always-on and the new wearable core
Recently, I mentioned smartphone SoCs consume one, maybe two orders of magnitude too much power for broader use in wearables. However, that is only when they are “on”. To save power and stretch battery life, smartphones spend a lot of time napping – display off, sitting still with MEMS sensors powered down, waiting for an incoming… Read More
Will 50% of New High Performance Computing (HPC) Chip Designs be Multi-Die in 2025?