Then, Python walked in for verification

Then, Python walked in for verification
by Don Dingee on 07-31-2014 at 12:00 am

Go ahead – type “open source” into the SemiWiki search box. Lots of recent articles on the IoT, not so many on EDA tools. Change takes a while. It has only been about five years since the Big Three plus Aldec sat down at the same table to work on UVM. Since then, Aldec has also gotten behind OS-VVM, and is now linked to a relatively new open… Read More


Wipe that smile off your device

Wipe that smile off your device
by Don Dingee on 07-30-2014 at 8:00 am

Privacy is a tough enough question when using a device – but what about when we’re done with it? In a world of two year service agreements with device upgrades and things being attached to long-life property like cars and homes, your data could fall into the hands of the next owner way too easily.

“Oh, it’s OK, I wiped the phone with a factory… Read More


CEVA creating a wearable IP platform

CEVA creating a wearable IP platform
by Don Dingee on 07-25-2014 at 12:00 am

Processor and GPU cores usually get the limelight, driven by the ARM and Imagination machines occupying the center square of most SoC designs. CEVA has quietly been assembling DSP IP in most of the squares around the edge, and may have just reached critical mass for wearables and IoT devices.… Read More


NoCs for system-level power management

NoCs for system-level power management
by Don Dingee on 07-23-2014 at 7:00 am

Most of the buzz on network-on-chip is around simplifying and scaling interconnect, especially in multicore SoCs where AMBA buses and crossbars run into issues as more and more cores enter a design. Designers may want to explore how NoCs can help with a more power-aware approach.… Read More


Thread is why Nest has extra 802.15.4 goodies

Thread is why Nest has extra 802.15.4 goodies
by Don Dingee on 07-15-2014 at 4:00 pm

From last week: “Chipmakers can’t afford to wait on the sidelines, hoping their standard fare gets picked up and fits in with one of these [#IoT]teams.” This week, it’s ARM, Freescale, and Silicon Labs joining with Google and others on Thread. Yet another consortium? A lot more to this story.… Read More


Chip side of the Open Interconnect Consortium

Chip side of the Open Interconnect Consortium
by Don Dingee on 07-09-2014 at 9:00 pm

Maybe it’s my competitive analysis gene, or too many years spent hanging out with consortium types, but I’m always both curious and skeptical when a new consortium arises – especially in a crowded field of interest. The dynamics of who aligns with a new initiative, and how they plan to go to market compared to other entities, prompts… Read More


Fantasy Tech-Ball and the Intel Rumor Wire

Fantasy Tech-Ball and the Intel Rumor Wire
by Don Dingee on 07-06-2014 at 9:00 am

Reading Intel analysis lately has been a lot like reading fantasy baseball analysis. Intel should buy Altera. Intel should waive Atom. Intel should fab for Apple. All of those have a near-zero probability of happening IMHO, and yet pundits continue to pitch their version of alternate reality, dealing away product lines and strategies… Read More


A song of optimization and reuse

A song of optimization and reuse
by Don Dingee on 07-01-2014 at 10:00 am

If you hang around engineers for any time at all, the word optimization is bound to come up. The very definition of engineer is to contrive or devise a solution. With that anointing, most engineers are beholden to the idea that their job is creating, synthesizing, and perfecting a solution specifically for the needs of a unique situation.… Read More


I’ll be with you in a second

I’ll be with you in a second
by Don Dingee on 06-27-2014 at 3:00 pm

One aspect of always-on is power conservation, being able to respond to events without having a device constantly in full-power mode. This month, the announcement of the Amazon Fire Phone and details revealed about the Google Android Wear SDK suggest another important dimension: the competitive advantage of rapid, frictionless… Read More


Real FPGAs don’t eat fake test vectors

Real FPGAs don’t eat fake test vectors
by Don Dingee on 06-26-2014 at 8:00 am

Vector blasting hardware is as old as digital test methodology itself. In the days of relatively simple combinational and finite state machine logic, a set of vectors aimed broadside at inputs could shake loose most faults with observable outputs. With FPGAs, creating an effective set of artificial test vectors has become a lot… Read More