Cadence invited Francois Lemery of ST Microelectronics to speak at a luncheon last Monday at DAC about designing for the 20nm node using module generators. Here are my trip report notes:
ST using Cadence IC Tools with Module Generators
Author: Daniel Payne
Schematic, IC Layout, Clock and Timing Closure from ICScape
Before this DAC I had never even heard of ICScape, so on Monday and Wednesday I visited their booth to find out their story.
Steve Yang, Ph.D. (Co-founder and President), Ravi Ravikumar (Marketing)
ICScape was founded in 2005 in Santa Clara by Steve Yang (Circuit Design engineer for microprocessor, Synopsys) and Jason Xing (Sun… Read More
Fast Monte Carlo and Analog Fast SPICE
Britto Vincent of ProPlus Design Solutions met with me at DAC on Monday morning to talk about Design For Yield (DFY) and Analog Fast SPICE.
In 2011 ProPlus announced DFY tools where the technology came from IBM, it provides fast Monte Carlo results up to 3 sigma, then added NanoSpice for faster simulation results. Similar in approach… Read More
Collaboration at 28nm, 20nm and 14nm
Wednesday morning I attended a panel discussion with: ARM, IBM, Cadence, GLOBALFOUNDRIES and Samsung.
The panelists all sang the same song of collaboration between EDA, IP and Foundry to enable 28nm, 20nm and even 14nm.… Read More
Physical IP Not From ARM or Synopsys
ARM and Synopsys are well-known physical IP companies however at DAC today I met with a lesser-known company named DXCORR that has some unique offerings for cache, multi-port memory and standard cell kicker libraries. I met with:… Read More
DAC 2012 – Sunday Night Kick Off
I arrived to a sunny San Francisco this afternoon, checked into my hotel then visited Moscone Center to pick up my Independent Media credentials. On the walk over I passed by Yerba Buena Gardens.… Read More
Two New Board Members at Mentor Graphics
One year ago the annual share holder meeting at Mentor Graphics had tight security, a no-camera policy, and the drama of Carl Icahn the corporate raider successfully adding three new board members. Fast forward to today where two of Icahn’s board members were not even nominated, and Mentor added two new board members. I chatted… Read More
SystemVerilog 2012 at DAC
I first met Stuart at Mentor Graphics back in 1995 or so, and he is one of the most knowledgable persons around for all things Verilog.
Stuart Sutherland is the editor for the IEEE 1800 SystemVerilog standard, so if you’re attending DAC and care about SystemVerilog then consider attending the Birds of a Feather meeting held… Read More
3D Transistors and IC Extraction Tools
Have you ever heard of a Super Pillar Transistor? It’s one of many emerging 3D transistor types, like Intel’s popular FinFET device.
In the race to continuously improve MOS transistors, these new 3D transistor structures pose challenges to the established IC extraction tool flows.
Foundries have to provide an Effective… Read More
Analog FastSPICE added to Tanner EDA
Last year when I visited Tanner EDA at DAC I heard about how they integrated the Analog FastSPICE circuit simulator from Berkeley DA.
This made sense to me because BDA has a good reputation for speeding up SPICE without compromising on accuracy, and Tanner users may want to mix and match tools from multiple EDA vendors.
This year they’ve… Read More
Facing the Quantum Nature of EUV Lithography