EDA revenues for Q2 2012 were up 10.8% compared to Q2 2011 as reported by EDAC today.
Increasing
- CAE
- IC Physical Design & Verification
- Semi IP
EDAC Reports Upbeat Q2 2012 Revenues
Author: Daniel Payne
High Frequency Analysis of IC Layouts
IC designers of passive devices often use empirical approaches to perform High Frequency Analysis (HFA), however there is at least one new approach being offered by Mentor Graphics using a tool flow of:
- Device detection and extraction with Calibre LVS and Calibre PERC
- Interconnect RLC extraction with Calibre xRC, Calibre xACT-3D
User Review: iOS 6 on iPad
Much has been written about the new iPhone 5 and iOS 6 in terms of the features, specifications, bill of materials, and chips used in the design. Today I’ll share my experiences of actually using the new iOS 6 on iPad as an EDA blogger.
Upgrading to iOS6
Clicking the On button and noticing that the App Store icon has something new,… Read More
A Brief History of RTL Design
RTL is an acronym for Register Transfer Level and refers to a level of hardware design abstraction using Registers and logic gates. Here’s an example schematic showing one DFF as a register, and one inverter as a logic gate.
Figure 1: RTL diagram of a DFF (D Flip Flop) and Inverter… Read More
Mentor Graphics Update at TSMC 2012 OIP
What
In just 20 days you can get an update on four Mentor Graphics tools as used in the TSMC Open Innovation Platform (OIP). Many EDA and IP companies will be presenting along with Mentor, so it should be informative for fabless design companies in Silicon Valley doing business with TSMC.
… Read More
Displaced but Looking to Add EDA Tools Skills?
In this tough economy you may find yourself displaced and looking for the next opportunity. If you’d like to add some new EDA tool skills, then check out what EMA Design Automation is offering with free Cadence OrCAD training.… Read More
Schematic Capture, Analog Fast SPICE, and Analysis Update
At the DAC show in June I met with folks at Berkeley DA and heard about their Analog Fast SPICE simulator being used inside of the Tanner EDA tools. With the newest release from Tanner called HiPer Silicon version 15.23 you get a tight integration between:… Read More
ASIC Prototyping with 4M to 96M Gates
I’ve used Aldec tools like their Verilog simulator (Riviera PRO) when teaching a class to engineers at Lattice Semi, so to get an update about the company I spoke with Dave Rinehart recently by phone. A big product announcement by Aldec today is for their ASIC prototyping system with a capacity range of 4 Million to 96 Million… Read More
SemiWiki on Android
This morning I got to try out the new Android app for SemiWiki, so this is something that you will benefit from as you’re on the go with an Android phone and want to stay up to date. It’s an intuitive app, so you’ll be up and running within minutes. My first step was to visit the Play Store, search for the app using “Semiwiki”,… Read More
Custom IC and AMS Tool Flow with Synopsys
The big three EDA companies all have Custom IC and AMS tool flows as shown in the following comparison table:… Read More
Facing the Quantum Nature of EUV Lithography