Author: Daniel Payne

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Who is Blogging at Cadence?

Who is Blogging at Cadence?
by Daniel Payne on 09-20-2013 at 1:31 pm
Categories: Cadence, EDA

As a blogger in the EDA industry I get to write every week, however I also end up reading every blog on SemiWiki plus multiple other sites to keep current on what’s happening in our business. I thought that it would be informative to look at Cadence Design Systems and how they are using blogging to talk not just about their own EDA… Read More

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Cutting Debug Time of an SoC

Cutting Debug Time of an SoC
by Daniel Payne on 09-19-2013 at 2:26 pm
Categories: EDA

The amount of time spent debugging an SoC dwarfs the actual design time, with many engineering teams saying that debug and verification takes about 7X the effort as the actual design work. So any automation to reduce the amount of time spent in debug and verification would directly impact the product schedule in a big way.

An example… Read More

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A Brief History of Magillem

A Brief History of Magillem
by Daniel Payne on 09-19-2013 at 1:17 pm
Categories: EDA, Magillem

Founders

Cyril Spasevski is the President, CTO and founding engineer at Magillem, bringing a team of engineers, all experts with an SoC platform builder tool. In 2006 Cyril and his team met a seasoned business woman, and decided to form Magillem. Design teams were struggling with different tools at different stages of the flow,… Read More

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A Hybrid Test Approach – Combining ATPG and BIST

A Hybrid Test Approach – Combining ATPG and BIST
by Daniel Payne on 09-09-2013 at 5:18 pm
Categories: EDA

In the world of IC testability we tend to look at various approaches as independent means to an end, namely high test coverage with the minimum amount of test time, minimum area impact, minimum timing impact, and acceptable power use. Automatic Test Pattern Generation (ATPG) is a software-based approach that can be applied to any… Read More

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Test Compression and Hierarchy at ITC

Test Compression and Hierarchy at ITC
by Daniel Payne on 09-09-2013 at 8:00 am
Categories: EDA, Synopsys

The International Test Conference (ITC) is this week in Anaheim and I’ve just learned what’s new at Synopsys with test compression and hierarchy. Last week I spoke with Robert Ruiz and Sandeep Kaushik of Synopsys by phone to get the latest scoop. There are two big product announcements today that cover:… Read More

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Low-Power Design Webinar – What I Learned

Low-Power Design Webinar – What I Learned
by Daniel Payne on 09-02-2013 at 7:00 pm
Categories: Ansys, Inc., EDA

You can only design and optimize for low-power SoC designs if you can actually simulate the entire Chip, Package and System together. The engineers at ANSYS-Apachehave figured out how to do that and talked about their design for power methodology in a webinar today. I listened to Arvind Shanmugavel present a few dozen slides and… Read More

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Low-Power Design Analysis and Optimization for Mobile and High-Performance Computing Applications

Low-Power Design Analysis and Optimization for Mobile and High-Performance Computing Applications
by Daniel Payne on 08-23-2013 at 7:36 pm
Categories: Ansys, Inc., EDA

For several decades now consumers like me have enjoyed using mobile devices including:

  • Transistor radios, my first one had just 6 discreet transistors in the 1960’s
  • HP 21 Calculator, used in college with Reverse Polish Notation, circa 1976
  • Zenith Data Systems laptop, with two floppy drives, 1980’s
  • Palm Pilot V,
… Read More
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Web-based Circuit Design and Analysis

Web-based Circuit Design and Analysis
by Daniel Payne on 08-21-2013 at 11:27 am
Categories: EDA

Last month I blogged about CircuitLaband received some two dozen comments, so clearly there is keen interest in using web-based tools for electronic circuit design and using the cloud to save designs plus run simulations. Today I’m reporting on TINACloud, provided by a company called DesignSoft. … Read More

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Why Adopt Hierarchical Test for SoC Designs

Why Adopt Hierarchical Test for SoC Designs
by Daniel Payne on 08-15-2013 at 4:37 pm
Categories: EDA, Synopsys, TSMC

IC designers have been creating with hierarchy for years to better manage large design sizes, however for the test world the concept of hierarchy and emerging standards is a bit newer. TSMC and Synopsys jointly created a webinarthat addresses hierarchical test, so I’ve attended it this week and summarized my findings here.… Read More

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Accelerating SoC Simulation Times

Accelerating SoC Simulation Times
by Daniel Payne on 08-15-2013 at 2:43 pm
Categories: Aldec, EDA, FPGA

There never seems to be enough time in a SoC project to simulate all of the cycles and tests that you want to run, so any technique to accelerate each run is welcomed. You can just wait for your software-based RTL simulator to finish running, or you can consider using a hardware-based accelerator approach. I learned more about one such… Read More