On Sunday night at DAC this week I sat in the front row and listened to Gary Smith give his predictions about EDA and IP as an industry. His financial forecast was a $6.8B industry in 2015, growing to $9B in 2019. An ideal company for Wall Street to invest in would have slow and steady growth. If you add semiconductor IP into the forecast… Read More
Author: Daniel Payne
Turning the Automotive Development Process Upside Down
Most of us drive automobiles and have a vague idea that the development of our cars takes many years, millions of dollars, is a proprietary process and require huge factories to produce. A relatively new company called Local Motors founded in 2007 has started to turn the automotive development process upside down because they do… Read More
Logic Synthesis Reborn
Combine the pressures of Moore’s Law which enable billion transistor SoCs and the shortened time to market from consumer electronics product cycles and you have the perfect storm for EDA tool vendors. A modern SoC can have 500 or more blocks, creating both a design and verification challenge. How in the world do you write … Read More
Even More Integration and Automation for ARM-based Designs
The attraction to an IP-based design methodology is that you can assemble an SoC from ready-made IP blocks, saving you valuable engineering development and verification time, while reducing risks from having to develop something from scratch and hoping that they meet industry standard specs. ARM is well known for supplying … Read More
The State of Desktops, Notebooks and Tablets
The personal computing market started out back in the late 1970’s, with IBM being a relative late-comer in 1981, however over many decades we’ve seen the unit volumes steadily increasing each year driving demand of semiconductors of all types. IC Insights is a research company that follows the personal computer … Read More
NVIDIA and Qualcomm Talk about High Level Synthesis, Samsung on Low Power for Mobile
Since 1978 I’ve seen many trends in the semiconductor design world: transistor-level IC design, gate-level design, RTL coding, High Level Synthesis (HLS) and IP re-use. We’ve witnessed the growth in design productivity enabling chips starting with just thousands of transistor all the way up to billions of transistors… Read More
Getting the Best Dynamic Power Analysis Numbers
On your last SoC project how well did your dynamic power estimates match up with silicon results, especially while running real applications on your electronic product? If your answer was, “Well, not too good”, then keep reading this blog. A classical approach to dynamic power analysis is to run your functional testbench… Read More
Design Collaboration, Requirements and IP Management at #52DAC
For SoC designers attending DAC in June you probably want to check out the EDA vendors that enable design collaboration among your engineers and designers that are spread out across a building, campus or the globe. Dassault Systemes does offer tools and methodologies for: Design collaboration, requirements and IP management.… Read More
Saving Time and Money on Your Next SoC Project
Every SoC project that I know of wants to finish on time, under budget, and maximize profits per device. When I first started out doing DRAM design I learned that we could maximize profit by doing shrinks of existing designs, move from ceramic to plastic packages, and reduce the amount of time spent on a tester. Today, the economic … Read More
DAC, IP, Parties and Philanthropy
My typical DACtrip is a blur of non-stop interviews with EDA, IP and Semiconductor vendors followed by a few dozen blogs to share what I’ve learned. I just became aware of something a bit different at DAC this year by talking with Jill Jacobs, an organizer for an event dubbed Heart of Technology (HoT) where they raise money for… Read More
Facing the Quantum Nature of EUV Lithography