AI, Machine Learning, Deep Learning and neural networks are all hot industry topics in 2019, but you probably want to know if these concepts are changing how we actually design or verify an SoC. To answer that question what better place to get an answer than from a panel of industry experts who recently gathered at DVcon with moderator… Read More
Author: Daniel Payne
IC Implementation Improved by Hyperconvergence of Tools
Physical IC design is a time consuming and error prone process that begs for automation in the form of clever EDA tools that understand the inter-relationships between logic synthesis, IC layout, test and sign-off analysis. There’s even an annual conference called ISPD – International Symposium on Physical Design… Read More
DAC56 Keynotes and SKYtalks – The Big Picture
Many of us have engineering degrees and are well paid to maintain a deep but narrow focus into a specific domain, but what about the big picture, like industry trends and emerging challenges? Well, DAC56 has just the thing to deliver us a front row seat to the big picture, and it’s contained in both the Keynotes and SKYtalks.… Read More
Functional Verification using Formal on Million Gate Designs
Verification engineers are the unsung heroes making sure that our smart phone chips, smart watches and even smart cars function logically, without bugs or unintended behavior. Hidden bugs are important to uncover, but what approach is best suited for this challenge?
With the Universal Verification Methodology (UVM) there’s… Read More
Cloud-based Functional Verification
The big three EDA vendors are constantly putting more of their tools in the cloud in order to speed up the design and verification process for chip designers, but how do engineering teams approach using the cloud for functional verification tests and regressions? At the recent Cadence user group meeting (CDNLive) there was a presentation… Read More
A Smarter Way to Do Multi-Board PCB Systems
Many electronic product ideas start out as sketches on the back of a napkin, then migrate over to diagrams drawn in Visio or PowerPoint, finally entered into EDA-specific tools. With that methodology there’s a big disconnect between the diagrams drawn with a purely graphical tool and the EDA tools, because there’s… Read More
Attend Parts of DAC For Free, Really
The Design Automation Conference (DAC) is the must-see, annual event for semiconductor professionals that design chips, use EDA software, and buy semiconductor IP. Like all conferences there’s an entrance fee, but for the 11th year now you can get a free pass, courtesy of three sponsors: Avatar Integrated Systems, ClioSoft… Read More
Traceability and Design Verification Synergy
The IC design and verification process can be comprised of many independent point tools, or for more synergy you can have tools that work together by a more synergistic process. We’ve all heard the maxim, “Work smarter, not harder.” A white paper just came out from Methodics on a smarter approach, Traceability… Read More
Ultra low-power Analog Design using a Multi-Project Wafer approach
On SemiWiki we often talk about bleeding-edge technology like 7nm, 5nm or even 3nm, but for analog IC designs there’s a low-cost alternative to getting your ideas validated and prototyped without taking out a multi-million dollar loan, and that’s through the use of Multi-Project Wafers (MPW). Starting with a mature… Read More
Data Centers and AI Chips Benefit from Embedded In-Chip Monitoring
Webinars are a quick way to come up to speed with emerging trends in our semiconductor world, so I just finished watching an interesting one from Moortec about the benefits of embedded in-chip monitoring for Data Center and AIchip design. My first exposure to a data center was back in the 1960s during an elementary school class where… Read More
Rapidus, IBM, and the Billion-Dollar Silicon Sovereignty Bet