According to a recent engineering survey, completing IC designs on time and within specifications gets exponentially more challenging with each node. Why? Here are the top five reasons:… Read More
Author: Daniel Nenni
SNUG 2017 Keynote: Aart de Geus on EDA Fusion!
I spoke with Aart before his SNUG keynote and found him to be very relaxed and upbeat about EDA and our future prospects which reminded me of my first ever (cringe-worthy) blog, “EDA is Dead”. Now, eight years later, we have what Aart calls “EDA Fusion” to thank for the reemergence of EDA as a semiconductor superpower, absolutely.… Read More
eFabless Design Challenge Results!
Will community engineering work for semiconductors? Will anyone show up? Well, the efabless design challenge is complete and the results are both interesting and encouraging, absolutely!
Efabless completed its low power voltage reference IP design challenge on Monday, March 13. This was a very interesting event that we followed… Read More
Samsung Should Just Buy eSilicon Already!
As you all know I’m a big fan of the ASIC business dating back to the start of the fabless semiconductor transformation where anybody could send a design spec to an ASIC company and get a chip back. The ASIC business model also started the smart phone revolution when Samsung built the first Apple SoCs for the iPhones and iPads.
Today … Read More
Succeeding with 56G SerDes, HBM2, 2.5D and FinFET
eSilicon presented their advanced ASIC design capabilities at a seminar last Wednesday evening. This event was closed to the press, bloggers and analysts, but I managed to get some details from a friend who attended. The event title was: “Advanced ASICs for the Cloud-Computing Era: Succeeding with 56G SerDes, HBM2, 2.5D and FinFET… Read More
TSMC Talks About 22nm, 12nm, and 7nm EUV!
The TSMC Symposium was jam-packed this year with both people and information. I had another 60 minutes of fame in the Solido booth where I signed 100 books, thank you to all who stopped by for a free book and a SemiWiki pen. SemiWiki bloggers Tom Dillinger and Tom Simon were also there so look for more TSMC Symposium blogs coming in the… Read More
ClioSoft Crushes it in 2016!
If you are designing chips in a competitive market with multiple design teams and IP reuse is a high priority then you probably already know about the ClioSoft SOS Platform. What you probably did not know however is how well they are doing with the re-architected version of their integrated design and IP management software.
We have… Read More
CEO Interview: Alan Rogers of Analog Bits
It has been incredible to watch the Semiconductor IP market grow from millions to billions of dollars during my career in Silicon Valley. In fact, more than half of my professional experience involves IP so when I talk about what it takes to be successful it is certainly worth a listen.
In my opinion the key ingredient to a successful… Read More
TSMC Design Platforms Driving Next-Gen Applications
Coming up is the 23rd annual TSMC Technology Symposium where you can get first-hand updates on advanced and specialty technologies, advanced backend capabilities, future development plans, and network with hundreds of TSMC’s customers and partners. This year the Silicon Valley event kicks off at the Santa Clara Convention… Read More
EUV is NOT Ready for 7nm!
The annual SPIE Advanced Lithography Conference kicked off last night with vendor sponsored networking events and such. SPIE is the international society for optics and photonics but this year SPIE Advanced Lithography is all about the highly anticipated EUV technology. Scotten Jones and I are at SPIE so expect more detailed… Read More
An Insight into Building Quantum Computers