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When it comes to functional verification of large designs, huge progress is being made in emulation and FPGA-based prototyping (about which I’ll have more to say in follow-on blogs), but simulation still dominates verification activity, all the way from IP verification to gate-level signoff. For many, while it is much slower… Read More
DVCon 2017 is a big week for Cadence verification announcements. They just released their Xcelium simulation acceleration product (on which I have another blog) and they have also released their latest and greatest prototyping solution in the Protium S1. This is new hardware based on Virtex UltraScale FPGAs on Cadence-designed… Read More
When you think about working with an ASIC service provider like Open-Silicon, you probably think about handling all the architecture, design and verification/validation in your shop, handing over a netlist and some other collateral, then the ASIC services provider takes responsibility for implementation and manufacturing.… Read More
We’ve become pretty good at reducing power in IoT edge devices, to the point that some are expected to run for up to 10 years on a single battery charge. But what if you wanted to go lower still or if, perhaps, your design can’t push power down to a level that would meet that goal? One area in systems where it can be challenging to further … Read More
You’d expect Mentor to be covering a lot of bases at DVCon and you wouldn’t be wrong. They’re hosting tutorials, a lunch, papers, posters, there’s a panel and of course they’ll be on the exhibit floor. I’ll start with an important tutorial that you really should attend, Monday morning, on creating Portable Stimulus Models… Read More
EDA has always been a fiercely competitive market, no more so than in emulation where the clash of claims and counter-claims can leave those of us on the sidelines wondering who’s really on top. Sales are the obvious indicator but leadership there flips back and forth between product releases. That makes Mentor’s choice to play … Read More
If there’s anyone out there who still doesn’t accept the importance of static RTL verification in the arsenal of functional verification methods, I haven’t met any recently. That wasn’t the case in my early days in this field. Back then I grew used to hearing “I don’t make mistakes in my RTL”, “I’ll catch that in simulation”, “My editor… Read More
I mentioned adversarial learning in an earlier blog, used to harden recognition systems against bad actors who could use slightly tweaked images to force significant misidentification of objects. It’s now looking like methods of this nature aren’t just an interesting sidebar on machine learning, they are driving major advances… Read More
DVCon is fast approaching, less than 3 weeks away. As a verification geek, this must be one of my favorite conferences, so I’ll be there; you’ll see me at tutorials, presentations and wandering around the Exhibit hall. (Pictures here from the 2016 DVCon – many of the same attendees will be at this year’s conference after all :cool:)… Read More
Cadence recently hosted a summit on embedded neural nets, the second in a series for them. This isn’t a Cadence pitch but it is noteworthy that Cadence is leading a discussion on a topic which is arguably the hottest in tech today, with this range and expertise of speakers (Stanford, Berkeley, ex-Baidu, Deepscale, Cadence… Read More
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Flynn Was Right: How a 2003 Warning Foretold Today’s Architectural Pivot