Daniel is joined by John Ferguson, senior director of product management for the Calibre products in the 3DIC space at Siemens EDA. He manages the vision and product offerings in the Calibre domain for 3DIC design solutions.
Dan explores the challenges of 3DIC and chiplet-based design with John, who describes the broad range of… Read More
In a prior post, I discussed how the clock is no longer just another signal at advanced nodes. Indeed, it is the most critical network on the chip. An optimized clock network can be the margin of victory for your next design. But extracting these benefits is challenging. The clock network is quite sensitive, and optimization can come… Read More
Our good friend Scotten Jones wrote a paper on a product that has been in joint development with Synopsys and is now available. Scott is currently President Semiconductor Manufacturing Economics and Senior Fellow at TechInsights. Scott and I have discussed this product many times and I feel it is ground breaking technology for… Read More
There’s more than one way to build a quantum computer (QC) though it took me a while to find a good reference. I finally settled on Building Quantum Computers: A Practical Introduction. Excellent book but designed only for those who will enjoy lots of quantum math. I’m going to spare you that and instead describe a couple of the more… Read More
Building a complex SoC is a risky endeavor that demands careful planning, strategic decisions, and collaboration across hardware and software domains. As highlighted in Darren Jones’ RISC-V Summit presentation from Andes Technology, titled “From Blueprint to Reality: Navigating SoC Tradeoffs, IP, and Ecosystem,”… Read More
This is not about architecting a full SoC from scratch. You already have a competitive platform, now you want to add some kind of accelerator, maybe video, audio, ML, and need to explore architectural options for how accelerator and software should be partitioned, and to optimize PPA. Now we have AI to help us optimize you’d like … Read More
MachineWare, and Andes Technology today announced a collaborative co-emulation solution designed to address the increasing complexity of RISC-V-based chip design. The solution integrates MachineWare’s SIM-V virtual platform, S2C’s Genesis Architect and Prodigy FPGA Prototyping Systems, and Andes’ high-performance… Read More
In the evolving landscape of telecommunications, uncrewed aerial vehicles (UAVs) are emerging as innovative platforms for extending 5G networks, particularly in areas lacking terrestrial infrastructure. Dr. Jyrki T. J. Penttinen’s paper, presented at the First International Conference on AI-enabled Unmanned … Read More
Electrical rule checking (ERC) is a standard part of any design flow. There is a hidden problem with the traditional approach, however. As designs grow in complexity, whether full-custom analog, mixed-signal, or advanced-node digital, the limitations of traditional ERC tools are becoming more problematic. This can lead to… Read More
Quantum Computing Technologies and Challenges