ASIC Design Engineer
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Website Mixel
About the Job
- Develop a thorough understanding of system-level design specifications
- RTL Coding/Synthesis of the digital part of Mixed Signal IPs
- Develop behavioral models for the analog parts of Mixed Signal IPs
- Develop advanced verification environment and test-bench components
- Working with the mixed signal team on the co-simulation and verification of the IPs
- Hardware verification of the digital module using cutting edge FPGA kits
Job Requirements
- Bachelor’s degree of Electronics Engineering. Master’s Degree is a plus
- 0-3 Years of experience in VLSI Digital Design/Verification, gate verification techniques is a plus
- Strong knowledge of Verilog RTL design/simulation
- Knowledge of ASIC/FPGA design flows including RTL Synthesis, Place and Route, and Timing Sign-off
- Knowledge of Unix/Linux operating system is a plus
- Knowledge of shell scripting/programming languages is a plus
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