Digital Verification Development Senior Engineer

About the Job

• Hands-on experience with employing constrained-random coverage driven verification methodology using UVM
• Participating in deploying new methodologies to improve coverage and execution time in collaboration with other experienced engineers on the team
• Working with the design team to validate and verify any requested design changes throughout the project life cycle.
• Develop test plan from specification and architect system-level verification environments.
• Develop test-bench components and coverage metrics.
• Execute RTL/Gate level simulations and analyze results.
• Work with the mixed-signal team on the co-simulation and verification of mixed-signal IPs.
• Contribute to design/verification process automation.

Job Requirements

• B.Sc. or M.Sc. in Electronics Engineering
• 3+ Years of experience in developing SV-based verification environments. 
• Strong knowledge of Verilog, System Verilog, and object-oriented 
• Computer skills required: Unix/Linux operating system
• Strong knowledge of Verilog, System Verilog, and object-oriented programming languages
• Knowledge of at least one standard verification methodology (such as VMM, OVM, or UVM)
• Familiarity with RTL design, synthesis, and CDC analysis is a plus
• Working knowledge of shell, Perl, and TCL scripting is a plus