Which IP for FD-SOI Ecosystem?

We know that the best technology or product, even if it exhibits best in class and unmatched features, is almost of no use if lacking an ecosystem. If you think about a processor core, you will expect to find compatible communication bus and memories (inside the SoC) and operating system, compiler, debugger, etc. When dealing with a disruptive ASIC technology like FD-SOI, you will expect to have multiple sources for raw SOI wafers, at least double sourcing capability for processing these wafers and, last but not least, a solid IP ecosystem. If you can’t decree the creation of this IP ecosystem, you (the foundry or ASIC vendor) can certainly invest resource to internally develop the foundation IP (standard cell library or memory compiler). Your involvement in supporting or initiating the development of complexes IP by the best in class IP vendors will make the difference too.

Taking a look at this FD-SOI roadmap, extracted from the presentation made by Patrick Blouet from ST during IP-SoC “Which IP from FDSOI Ecosystem”, give you an idea of the additional features and related IP to be added to the current offer at 28nm FDSOI. Today the status is that you can design a complete digital SoC (for example an Application Processor), including high performance CPU and GPU (from ARM or Imagination Technologies), internal memories for cache, DDR4 memory controller (from Cadence) and the various IP to support interface protocols like USB, HDMI, MIPI and probably more.

The 28nm roadmap feature path gives you some interesting indication too. If RF IP can be available on the same IC to support WiFi, Smart BT or WigBee as well as some advanced mixed-signal function, you are close to build a dedicated IoT chip supporting smart watch or metering application. Then the designer could take full advantage of the power efficiency inherent to FD-SOI technology, and release to the IoT market an application offering strong differentiators in term of cost (monochip solution) and power consumption, thanks to FDSOI. On the below picture, ST claims for a power consumption improvement better than 3X between 40LP and 28 FDSOI.

This example of a SoC integrating RF and mixed-signal illustrate an IoT application, but a building a complete IP ecosystem will require to port many existing functions to FDSOI. At SOC level, migrating an existing design from bulk to planar FD represents an effort comparable to half-node migration, for example from 45nm to 40nm. In other words, it brings very worthwhile benefits at reasonable efforts. A typical approach could be:

• CPU and GPU: the main objective is maximum peak performance and the design is re-worked, making the most of Forward Body Bias (FBB);
• Other SOC blocks: the main objective is power savings, by reaching the target operating frequencies at lower Vdd; there is no change to block design, Timing Analysis is re-run and ECO (Engineering Change Order) is performed to fix violations if needed.
• Other IP such as IOs and PHY blocks are swapped for their planar FD counterpart.

During the presentation at IP-SoC, Patrick Blouet has unveiled THINGS2DO, the program supporting the FDSOI ecosystem creation:

The partners rank from Silicon suppliers, tools providers, IP & Design Houses, System integrators and research organizations. Developing IP supporting FD-SOI is a business driven decision, and we know that the more IP will be available, the higher will be the number of FD-SOI ASIC design-win. “Somebody“ has to initiate this virtuous cycle, and ST has decided to do it with THINGS2DO initiative. This decision is certainly the best THING to do at the moment, like giving a kick to start a motor, the market following when the business will become attractive enough. Because Samsung and Global Foundries are also in the loop, we have no doubt that this IP ecosystem will grow…

From Eric Esteve from IPNEST