FD-SOI at 14nm

At the recent Semicon West, Michel Haond of ST Microelectronics had a presentation on 14nm FD-SOI, or what they more lengthily call UTBB FD-SOI (which when you expand it all out comes to Ultra Thin Body and Buried-Oxide Fully Depleted Silicon on Insulator). When Chenming Hu (or whoever in his group) came up with the term FinFET it was certainly a much catchier name. Even legendary marketers Intel could only come up with TriGate, which doesn’t seem an improvement to me. Anyway, seems we are stuck with FD-SOI now.

As you probably know (at least if you have been following Semiwiki), bulk transistors ran out of steam at 20nm and we needed new transistor architectures. The two competitors are FinFET and FD-SOI. As ST pointed out, if you turn the FinFET on its side (see the diagram above) then the two transistors are not that different. The problem with bulk planar is that the channel is not well controlled by the gate and so leakage is unacceptably high since it is not possible to truly turn the transistor off. FinFET and FD-SOI both make the channel region very thin, FinFET by putting the gate on both sides (and the top) of the channel, FD-SOI by backing the channel with an insulator so there is no route for leakage current to sneak around the back.

ST Microelectronics has been manufacturing FD-SOI at 28nm and they have also licensed the technology to Samsung (and, perhaps, GlobalFoundries). It certainly seems to be a good way of extending 28nm, getting 20nm performance in a 28nm process. That is important since there is a lot of 28nm capacity but, more importantly, 28nm does not require double patterning.

In the presentation, Michel described 14nm FD-SOI as a 2-D bulk process with the same performance as a 3-D FinFET process. There are some significant potential advantages. Simpler process with fewer steps and fewer masks (but a more expensive base wafer). No channel doping, no pocket implants. Potential for back-bias control leading to being able to dynmaically adjust performance vs lower power. ST believe the process is scalable down to 10nm.

The presentation contains a lot of detail about process innovations, process performance boosters and process bosters that are too specialized to go into unless you are a die-hard TD engineer. But a couple of things to point out: there is local interconnect (middle-of-line MOL). M1/M2/M3 are double patterned with a 64nm pitch. Higher metal layers have 80nm pitch (or greater) and are single patterned. The N-transistors have a silicon channel with Hafnium Oxide Titanium Nitride oxide (HfO2/TiN). The P-transistors have Silicon Germanium channels.

The process has 18 masks for the FEOL (transistors), 7 masks for MOL (local interconnect) and 27 masks for BEOL (metal fabric) for 11 layers of metal. If you want all the gory details they are in the picture above.

The timeline for all this is: 28nm is available, 14nm is in development now and 10nm will be in R&D during 2015 and 2016. At 16nm, the expected performance improvement over the previous generation is either a 20% speedup or 30% power reduction at the same speed. At 10nm, either a 20% speedup or 25% power reduction at same speed.

Michel’s full presentation is here.

See also:
FD-SOI: 20nm Performance at 28nm Cost
FD-SOI Better Than FinFET?
Keywords: FD-SOI, Cost, FinFET

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