5 Rules of Power Management Using NoCs

If it has escaped your notice that power management on SoCs is important then you need to get out more. Increasingly, the complexity of the interconnect between the various processors, memories, offload processors, devices, interfaces and other blocks means that the best way to implement it is to use a network on chip (NoC). But without using the NoC optimally, the power dissipated will be much higher than it need to be. The NoC has a level of intelligence within itself, and this can be used, for example, to aggressively power down blocks safe in the knowledge that the NoC will never attempt to deliver data to a sleeping block without waking it.

So here are the five rules of power management using NoCs:

Rule 1: The NoC must be fast.

• A well designed network that is also very fast allows the synthesis tool to use high V[SUB]t[/SUB] transistors. Designs with a high percentage of high V[SUB]t[/SUB] transistors can achieve reductions of as much as 75% leakage power compared to the faster but leakier low V[SUB]t[/SUB]
• A fast NoC means that the synthesis constraints are less tight and so fewer and smaller buffers are required inside blocks resulting in further power saving

Rule 2: The NoC must support both coarse-grain and fine-grain clock gating

• Careful clock gating that is architected into the design will produce a much better result than simply relying on the synthesis tools. Results that clock gate more than 99.9% of the design can be achieved.
• Coarse grained clock gating gates entire branches of the clock tree, saving not just the energy suppressed in the unclocked flops but the power needed to drive the clock network itself. When the clock network can consume up to 30% of the power on a chip, this can lead to big savings.

Rule 3: The NoC must allow clock and power “domain boundaries” within the NoC

• Different clocks for different parts of the network.
• Different voltage supplies for different parts of the network.
• Portions of the network that can be idled or even powered off.
• Sensibly group blocks that are on the same clocks and power to minimize components required on each domain crossing (and the CDC checks required)

Rule 4: The NoC must be aware of the power state of network components.

• Catch traffic early that accesses powered down parts of the SoC.
• Allows network interfaces to tell the power manager when it is safe to remove power from a block.
• Two alternatives are available when a transaction is received for a component in the system that is powered off: a) reject the traffic (preferably at the source) or b) signal the system power manager that a power domain must be powered up.

Rule 5: Integrate auto-wake-up features into NoC.

• Network requests wake-up of necessary power domains, without software intervention.
• The alternative to rejecting the traffic is to use a high performance Wake-on-Demand system that can operate without SW intervention. Many SoCs have SW controlled system power management schemes that suffer from high latency. A HW based Wake-on-Demand mechanism operates in a few clock cycles and allows the initiator agent to signal for a wake-up and hold the transaction until it can be completed.

Following these rules means that the power can be significantly reduced compared to using alternative interconnect technologies. In particular, a sophisticated approach to powering down blocks can be undertaken without requiring the embedded software engineers to explicitly handle it. The NoC can take care of it, ensuring that no errors occur due to trying to communicate with a powered down block, something very difficult to guarantee with approaches where power down and power up is completely under software control. And another major power saving versus software control is that the (fairly power-hungry) processor does not need to be powered up all the time.

In April, ARM licensed 138 Sonics patents, some of them in these power areas. ARM has its own proprietary NoC technology Amba 4 AXI and ACE but coming relatively late to the NoC game, Sonics had already developed many of the fundamental technologies required for an effective NoC. They are also working with Sonics on their next generation NoC technology.

More information on Sonics’s 4th generation GHz NoC technology is here.