Making Your Next Chip Self-Aware

One holy grail of AI software developers is to create a system that is self-aware, or sentient. A less lofty goal than sentient AI is for chip designers to know how each specific chip responds to Process variations, Voltage levels and Temperature changes. If a design engineer knew exactly which process corner that each chip was fabricated under, then they could dynamically control each chip to perform in an optimal manner. If I knew how much current my transistors consumed with a simple test measurement, then I could predict which test bin they should fall into instead of running a complete functional test. If I could measure the performance of my transistors over time, then I could predict their performance during the aging process and make adjustments to the operating conditions. The list of benefits is quite long if only there was a method to measure the PVT characteristics of each chip.

Crafty engineers have figured out how to enable these benefits through something called embedded in-chip monitoring, placing special circuits onto each chip that can dynamically measure and report process variation, voltage levels and temperature values. Moortec is such a company that has commercialized on-chip monitoring and offering the SoC industry their IP application, integration and device test during production since 2005, based in Plymouth, UK.

Here are some reasons that you should consider adding embedded in-chip monitoring:

• Measure process variation per chip
• Dynamically measure voltage levels for VDD during chip operation
• Enable Dynamic Voltage and Frequency Scaling (DVFS) to control power consumption
• Support Adaptive Voltage Scaling (AVS) to manage power
• Optimize your CMOS designs from 40nm down to 7nm process nodes

As device geometries get smaller the variations in switching speed delays start to increase as a function of supply voltage, so knowing your internal VDD levels is critical to performance.

Switching speed delay variations against supply voltage for a number of different process technologies

Voltage threshold values shift over time caused by negative bias temperature instability (NBTI) and hot carrier injection (HCI), so being able to measure your Vt values over time is crucial for reliable operation.

V degradation due to NBTI and HCI

To learn more about embedded in-chip monitors from the experts at Moortec then you should consider attending their upcoming webinar online.

Webinar Details

• US, Europe – Wednesday, December 6, 6PM GMT (10AM PST)
• China, Taiwan, South Korea– Thursday, December 7, 8AM GMT (4PM CST)

Who Should Attend?
The webinar is aimed at IC developers and engineers working on advanced node CMOS technologies from 40nm down to 7nm, will also highlight the challenges posed by process, temperature and voltage variability and how those challenges relate to the stability of complex SoC designs. Moortec provide complete PVT Monitoring Subsystem IP solutions on 40nm, 28nm, FinFET and 7nm. As advanced technology design is posing new challenges to the IC design community, Moortec are able to help our customers understand more about the dynamic and static conditions on chip in order to optimize device performance and increase reliability. Being the only PVT dedicated IP vendor, Moortec is now considered a centre-point for such expertise.

About Moortec
Established in 2005, Moortec provide in-chip monitors and sensors, such as embedded Process Monitors (P), Voltage Monitors (V) and Temperature Sensors (T). Moortec’s PVT monitoring IP products enhance the performance and reliability of today’s Integrated Circuit (silicon chip) designs. Having a track record of delivery to tier-1 semiconductor and product companies, Moortec provide a quick and efficient path to market for customer products and innovations. For more information please visit www.moortec.com