In-Chip Monitoring Helps Manage Data Center Power

In-Chip Monitoring Helps Manage Data Center Power
by Tom Simon on 09-07-2020 at 6:00 am

in-chip sensing

Designers spend plenty of time analyzing the effects of process, voltage and temperature. But everyone knows it’s not enough to simply stop there. Operating environments are tough and have lots of limitations, especially when it comes to power consumption and thermal issues. Thermal protection and even over-voltage protections… Read More


Siemens Acquires UltraSoC to Drive Design for Silicon Lifecycle Management

Siemens Acquires UltraSoC to Drive Design for Silicon Lifecycle Management
by Mike Gianfagna on 07-07-2020 at 10:00 am

Some Key Executives from UltraSoC

As reported recently by Dan Nenni, Siemens has signed an agreement to acquire Cambridge, UK-based UltraSoC Technologies Ltd. We’ve all seen plenty of mergers and acquisitions in EDA.  Some transactions perform better than others. The best ones enhance an existing product or service by blending non-overlapping technologies.… Read More


Optimizing power and increasing data throughput in advanced multi-core AI/ML/DL devices

Optimizing power and increasing data throughput in advanced multi-core AI/ML/DL devices
by Daniel Nenni on 04-26-2020 at 8:00 am

If you are working on complex Artificial Intelligence (AI) or Machine Learning (ML) or Deep Learning (DL) designs using advanced node processes, you will understand the motivations for optimising CPU utilisation, device power and processing speed. Cutting-edge AI, ML & DL chips, by their very nature, are susceptible to… Read More


Data Centers and AI Chips Benefit from Embedded In-Chip Monitoring

Data Centers and AI Chips Benefit from Embedded In-Chip Monitoring
by Daniel Payne on 03-08-2019 at 12:00 pm

Webinars are a quick way to come up to speed with emerging trends in our semiconductor world, so I just finished watching an interesting one from Moortec about the benefits of embedded in-chip monitoring for Data Center and AIchip design. My first exposure to a data center was back in the 1960s during an elementary school class where… Read More


Improving Yield and Reliability with In-Chip Monitoring, there’s an IP for that

Improving Yield and Reliability with In-Chip Monitoring, there’s an IP for that
by Daniel Payne on 08-24-2018 at 12:00 pm

There’s an old maxim that you can only improve what you measure, so quality experts have been talking about this concept for decades and our semiconductor industry has been the recipient of such practices to such an extent that we can now buy consumer products that include chips with over 5 billion transistors in them. You’ve… Read More


Making Your Next Chip Self-Aware

Making Your Next Chip Self-Aware
by Daniel Payne on 12-01-2017 at 12:00 pm

One holy grail of AI software developers is to create a system that is self-aware, or sentient. A less lofty goal than sentient AI is for chip designers to know how each specific chip responds to Process variations, Voltage levels and Temperature changes. If a design engineer knew exactly which process corner that each chip was fabricated… Read More