WP_Term Object
    [term_id] => 121
    [name] => IROC Technologies
    [slug] => iroc-technologies
    [term_group] => 0
    [term_taxonomy_id] => 121
    [taxonomy] => category
    [description] => 
    [parent] => 14433
    [count] => 13
    [filter] => raw
    [cat_ID] => 121
    [category_count] => 13
    [category_description] => 
    [cat_name] => IROC Technologies
    [category_nicename] => iroc-technologies
    [category_parent] => 14433

SOCFIT, Circuit Level Soft Error Analysis

SOCFIT, Circuit Level Soft Error Analysis
by Paul McLellan on 05-13-2013 at 2:50 pm

I blogged recently about reliability testing with high energy neutron beams. This is good for getting basic reliability data but it is not really a useful tool for worrying about reliability while the chip is still being designed and something can be done about it.

That is where IROC Technologies SOCFIT tool comes in. It takes all the data from the type of silicon analysis with real neutrons, and uses it to analyze the way that the various cells on the chip have been hooked together to provide reliability estimates. SOCFIT quickly and accurately calculates the failure rate (FIT) and various derating factors for the SoC. It works from either an RTL or a gate-level representation of the design.

SOCFIT uses the foundry’s SER database for FIT and derating simulation. It can handle very large designs with tens of millions of flops. It then provides an extensive report detailing the contribution of each cell in the design to the overall FIT rate and details of derating. There is a smart fault injection simulation for application derating. SOCFIT is available as a tool but usually, at least the first time, design groups work with IROCtech experts to both get good results and to learn how to interpret them.

How much it is worth investing to make the design more reliable and less sensitive to SEE errors is an economic one, and depends on the end-market. Satellite electronics might justify triple redundancy and voting since they have to survive in a more hostile environment than on the ground. Making a cell-phone that reliable is just not worth the cost since they are not mission critical and will most likely crash regularly due to software bugs and other issues, not due to cosmic rays. And a phone only has to last a few years.

Automobile electronics is one of the areas most focused on reliability. Cars have to last for twenty years, operate in deserts and Alaskan winters, and while it doesn’t matter too much if your radio reboots due to a particle upset, the engine control ECU(s) are another thing. Medical electronics is another area which cannot tolerate much unreliability.

As transistors get smaller and smaller, and the power-supply voltages continue to decrease, the currents that high energy particles can induce are more and more likely to cause SEE upsets. So this isn’t a problem that is going away, it is a problem that is going to continue to get worse.

A case study on SOCFIT is here. The datasheet for SOCFIT is here.

IROCtech will be at DAC in booth #1738.

Share this post via:


0 Replies to “SOCFIT, Circuit Level Soft Error Analysis”

You must register or log in to view/post comments.