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Cell Level Reliability

Cell Level Reliability
by Paul McLellan on 04-03-2013 at 6:06 pm

I blogged last month about single event effects (SEE) where a semiconductor chip behaves incorrectly due to being hit by an ion or a neutron. Since we live on a radioactive planet and are bombarded by cosmic rays from space, this is a real problem, and it is getting worse at each process node. But just how big of a problem is it?

TFIT is a tool for evaluating all the cells in a cell-library, or the cells in a memory (or memory compiler) to calculate just how vulnerable they are to SEE causing a failure-in-time (FIT). It is very fast and the test results are within 15% for any type of cells. Within 15% of what? Within 15% of the actual value, which is determined by going to Los Alamos and putting real chips in a beam of neutrons so that damage is accelerated (or similar tests with alpha particles). IROC provide this as a service, btw, but that is a topic for another blog.

Since manufacturing silicon and bombarding it while designing a cell-library is not practical, TFIT is the way to get a “heat map” of where cells are vulnerable, in just the same way as we use circuit simulation to characterize the timing performance of the cells without having to manufacture them. Vulnerable transistors in the flop above, for example, are highlighted. The color corresponds to different linear energy transfer (LET) values. High energy particles only need to hit anywhere in the outer black rings, but, as you would intuitively expect, lower energy particles have to hit more directly as shown in red.

TFIT takes as input process response models (which today usually comes directly from the foundry since foundry A doesn’t really want foundry B analyzing their reliability data in detail). These are available for most recent processes in production at both TSMC and Global plus more generic models for older processes at 180nm, 90nm and 65nm. Along with that is iROC’s secondary particles nuclear database. The cell requires both layout and a spice netlist.

Memory analysis is a bit more complex since the bit cells are so small that a single particle can impact multiple bits, known as a multi-cell upset (MCU). The reliability data can then be used to decide on appropriate error correcting codes and how to organize the bits. Again, results are within 15%.

The tool can be run interactively on a single cell but it is often used in batch mode to characterize the vulnerability of an entire cell library. To analyze a single impact on an SRAM cell takes just a few seconds. The only comparable way to do analysis is to use TCAD which takes 4-8 hours. For more detail, which requires analyzing more than a single impact or a whole library, the TCAD approach is just not practical.


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