WP_Term Object
    [term_id] => 121
    [name] => IROC Technologies
    [slug] => iroc-technologies
    [term_group] => 0
    [term_taxonomy_id] => 121
    [taxonomy] => category
    [description] => 
    [parent] => 14433
    [count] => 13
    [filter] => raw
    [cat_ID] => 121
    [category_count] => 13
    [category_description] => 
    [cat_name] => IROC Technologies
    [category_nicename] => iroc-technologies
    [category_parent] => 14433

Soft Error Rate (SER) Prediction Software for IC Design

Soft Error Rate (SER) Prediction Software for IC Design
by Daniel Payne on 04-16-2012 at 10:00 am

My first IC design in 1978 was a 16Kb DRAM chip at Intel and our researchers discovered the strange failure of Soft Errors caused by Alpha particles in the packaging and neutron particles which are more prominent at higher altitudes like in Denver, Colorado. Before today if you wanted to know the Soft Error Rate (SER) you had to fabricate a chip and then submit it to a specialized testing company to see the Failure In Time (FIT) levels. It can be very expensive to have an electronic product fail in the field because of Soft Errors and the SER levels are only increasing with smaller process nodes.

Intel 2117, courtesy of www.cpumuseum.com

Causes of SER
Shown below are the three causes of SER:

  • neutrons found in nature can strike Silicon creating alpha particles
  • Impurities in packaging materials emit alpha particles
  • Boron impurities can create alpha particles

    When an alpha particle strikes the IC it can upset the charge in a memory cell or flip-flop, causing it to change states, leading to a temporary logic failure.

    SER Prediction Software
    The good news is that today a company called iROC announced two software tools that will actually allow IC designers to predict and pinpoint the layout and circuit locations that are most susceptible to high FIT levels.

    • TFIT (Transistor Failure In Time)
    • SOCFIT (SOC Failure in Time)

    The TFIT tool reads in something called a Response Model provided by the Foundry, your SPICE netlist, and GDS II layout, it then runs a SPICE circuit simulation using HSPICE or Spectre (can be adapted to work with Eldo, etc.). Output from TFIT is the FIT rate of each cell and it can show you which transistors are most triggered by neutron particles so that you can improve your design sensitivity. This simulation run takes tens of minutes.

    SRAM designers can add Error Correcting Codes (ECC) to their designs to mitigate FIT, however a Flip-Flop has no ECC so one choice is to harden the FF which creates a cell that is 2X or 3X the size and power.

    A FF netlist can be analyzed by TFIT in about 10-20 minutes.

    SER Data has the FIT info for all FF and SRAM cells, including combinational logic.

    SOCFIT can be run on either the RTL or gate-level netlist, and has a capacity of 10+ million FFs. It uses a static timing analysis tool (Synopsys Primetime, Cadence), and can also use simulation tools for fault injection (Synopsys, Cadence). It first runs a static analysis on RTL or gates to determine the overal FIT rate, if your design is marginal then you can run a dynamic analysis using fault injection (typical 10 hour run time). This approach could use emulation to speed up results in the future.

    The SOCFIT tool answers the question, “Which cells are the most sensitive in my design?”

    You can even run SOCFIT before final tapeout, while logic is changing. SOCFIT has been under development for 8 years now, and they’ve seen good correlation between prediction and actual measurement.

    SER Info
    Both memory and logic have SER issues, even FF circuits, but not so much combinational logic because of its high drive.

    One particle can upset multiple memory bits now in nodes like 40nm and smaller.

    SRAM is more sensitive to neutron particles than FFs, then DRAMs are less sensitive because alpha particles impact leakage.

    Flash memory is even less sensitive than DRAM to Single Event Upsets (SEU).

    The FPGA architecture is most sensitive to SER because of the heavy use of FF cells.

    Bulk CMOS is more sensitive than SOI.

    FinFET is new, so iROC is just starting to analyzing that from an R&D viewpoint using 3D TCAD models. You can expect to see more data later in the year.

    TFIT will cover all voltages, and process variations.

    TSMC provides the Response Model input to TFIT, and they have been providing the SER Data to customers based on testing in the past, not simulation.

    iROC – The Company
    iROC (Integrated RObustness On Chip) has a mission to analyze, measure and improve SER on ICs. They’ve been providing SER testing services since 2000, where they bring chips to a Cyclotron and expose them with Neutron beams to replicate 10 years of life in just minutes. iROC also partners with foundries like TSMC and GLOBALFOUNDRIES.

    Competition to the iROC approach are mostly internally developed R&D tools from IDMs.

    Some 500 chips have been tested so far, so iROC understands the problems and how to prevent them from being catastrophic.

    iROC is the first commercial EDA company to offer two SER analysis tools used at the cell and SOC levels, the tool results correlate well with actual measurements on silicon chips. This will be an exciting company to watch grow a new EDA tool category in the reliability analysis segment.

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