EDA Open Source and Free Tools Wiki

Published by Daniel Payne on 04-21-2020 at 1:54 pm
Last updated on 01-05-2023 at 10:05 pm

SYSTEM

PandA-bambu – framework for research in high-level synthesis and HW/SW co-design
QElectroTech – Electronic diagrams
SystemC – system design and modeling
WaveDrom – draws your Timing Diagram or Waveform from simple textual description

PCB

Electric – IC design with schematic capture, layout, routing, LVS, PCB layout
Fritzing – Schematic capture and PCB layout
gEDA – Schematic capture
Horizon EDA – Schematic and PCB layout
KiCad – PCB layout
KTechLab – Electronic and PIC microcontroller design
LibrePCB – PCB Layout
LTspice – SPICE simulation, schematic capture, waveform viewer, Analog Devices
PCB – PCB layout
pcb-rnd – PCB layout

IC

Alliance/Coriolis – VHDL compiler, simulator, logic synthesizer, automatic place and route
Amaranth – Python-based HDL toolchain
Animate – Virtuoso schematic users can quickly see an automated analog layout, freemium tool from Pulsic
CflexHDL – design digital circuits in C, simulate really fast with a regular compiler.
Chisel – Hardware compiler framework
cocotb – coroutine based co-simulation testbench environment for verifying
Covered – Verilog code coverage
VHDL and SystemVerilog using Python
CUGR – Global routing tool developed by CUHK
CVC – Circuit Validity Checker, for errors in CDL netlist.
Edalize – Python library for interfacing EDA tools (Icarus, Yosys, ModelSim, Vivado, Verilator, GHDL, Quartus)
Fault – Design for Test
FuseSoc – package manager and a set of build tools for HDL code.
Gaw – Gtk Analog Wave viewer
GDSfactory – Python library for GDS generation
GDSpy – Python module for creation and manipulation of GDS files
GHDL – G HDL, a VHDL analyzer, compiler, simulator and synthesizer
Glade – Gds, Lef And Def Editor – layout and schematic editor, DRC, extraction, LVS.
Gnucap – GNU Circuit Analysis Package
GtkWave – waveform plot tool for digital simulation
Icarus Verilog – Verilog simulator (free)
iic-osic – collection of useful scripts and documentation
ipyxact – Python based IP-XACT parser
IRSIM – switch-level simulator
KLayout – Mask layout tool
LibrEDA – place and route
LiteX – Migen/MiSoC based Core/SoC builder
Magic – IC layout, extraction, DRC
Makerchip-app – Desktop connection to free online Makerchip IDE
Migen – Python toolbox for HDL design
MyHDL – Python as a hardware description and verification language
Netgen – Layout Versus Schematic (LVS) tool
NetlistSVG – draws SVG netlist from Yosys JSON netlist
nMigen – Python based HDL design
Ngspice – SPICE circuit simulation
NVC – VHDL simulator and compiler
Open_PDKs – PDK setup scripts
OpenLane – digital RTL2GDS flow
OpenRAM – Memory compiler development framework
OpenROAD – RTL to GDS in 24 hours, no human in the loop
OpenSTA – Static Timing Analyzer
OpenVAF – Verilog-A compiler
Oregano – schematic capture and SPICE circuit simulation
OSVVM – A VHDL verification framework, utility library, verification component library, and a simulator independent scripting flow
Padring – padring generation tool
PipelineC – HLS using C
PyCell Studio – create PyCells with Python and OpenAccess
PyRTL – collection of classes for Pythonic RTL design
PySpice – interface Ngspice and Xyce from Python
PyVerilog – Python toolkit for Verilog
Qrouter – multi-level, over-the-cell maze router
Qucs – Quite Universal Circuit Simulator
RePlAce – global placement tool
Revolution EDA – Symbol and schematic editor, integration with Xyce for circuit simulation
RgGen – code generation tool for configuration and status registers
Risc-v toolchain – GNU compiler toolchain for RISC-V RV32! cores
SandPiper-SaaS – CLI connection to free (though proprietary) SandPiper™ microservice for TL-Verilog compilation.
SiliconCompiler – modular build system for hardware
sky130 – SkyWater Technologies 130nm CMOS PDK
SPEF-Extractor – A Python library that reads LEF and DEF files, extract RC parasitics then create a SPEF file
SpinalHDL – HDL that creates VHDL or Verilog
Spyci – analyze or plot ngspice or xyce output data with Python
Tbengy – Python tool for SV/UVM testbench generation and RTL synthesis, uses Vivado and Digilent FPGA boards
v2k-top – Verilog-AMS parser/simulation framework
Verilator – Verilog simulator
Vlog2Verilog – Verilog file conversion
WRspice – Circuit simulator.
XCircuit – Schematic capture for SPICE netlists and PostScript
Xschem – Schematic capture and netlisting: VHDL, Verilog, SPICE.
Xic – Schematic capture and IC layout editor.
Xyce – Parallel analog circuit simulator from Sandia National Laboratories
Yosys – Verilog RTL synthesis

FPGA

FOEDAG – Framework Open EDA Gui
fpga-bitstream – Generate a generica or fabric dependent bitstream
nextpnr – FPGA place and route
OpenFPGA – framework that enables rapid prototyping of customizable FPGA architectures
Project IceStorm – Lattice bitstream format documentation
Qflow – digital synthesis flow using Verilog or VHDL, targets Xilinx or Altera
Raptor – commercial FPGA flow for FPGA design, RapidSilicon
SymbiFlow – FPGA framework for tools, Verilog to bitstream
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