SYSTEM
PandA-bambu – framework for research in high-level synthesis and HW/SW co-design
QElectroTech – Electronic diagrams
SystemC – system design and modeling
Switchboard – framework for communication between distinct hardware models, such as RTL simulations, RTL on FPGAs and fast SW models.
WaveDrom – draws your Timing Diagram or Waveform from simple textual description
PCB
eSim – Circuit design, simulation, analysis, PCB design using KiCad, Ngspice, Verilator, Makerchip, GHDL and OpenModelica.
QSPICE – simulator, schematic capture and waveform viewer for RF and power circuits, free from Qorvo
IC
Amaranth – Python-based HDL toolchain
CflexHDL – design digital circuits in C, simulate really fast with a regular compiler.
cocotb – coroutine based co-simulation testbench environment for verifying
Covered – Verilog code coverage
VHDL and SystemVerilog using Python
CUGR – Global routing tool developed by CUHK
CVC – Circuit Validity Checker, for errors in CDL netlist.
Edalize – Python library for interfacing EDA tools (Icarus, Yosys, ModelSim, Vivado, Verilator, GHDL, Quartus)
Fault – Design for Test
Gaw – Gtk Analog Wave viewer
GDSfactory – Python library for GDS generation
GDSpy – Python module for creation and manipulation of GDS files
Glade – Gds, Lef And Def Editor – layout and schematic editor, DRC, extraction, LVS.
MyHDL – Python as a hardware description and verification language
NVC – VHDL simulator and compiler
Open_PDKs – PDK setup scripts
OpenLane – digital RTL2GDS flow
OSVVM – A VHDL verification framework, utility library, verification component library, and a simulator independent scripting flow
Padring – padring generation tool
PeakRDL – control and status register (CSR) toolchain.
PipelineC – HLS using C
PyCell Studio – create PyCells with Python and OpenAccess
PyRTL – collection of classes for Pythonic RTL design
PySlint – Python based SystemVerilog linter for testbenches, UVM, DPI and SVA.
PySpice – interface Ngspice and Xyce from Python
PyVerilog – Python toolkit for Verilog
RgGen – code generation tool for configuration and status registers
Risc-v toolchain – GNU compiler toolchain for RISC-V RV32! cores
SiliconCompiler – modular build system for hardware
sky130 – SkyWater Technologies 130nm CMOS PDK
SPEF-Extractor – A Python library that reads LEF and DEF files, extract RC parasitics then create a SPEF file
Spyci – analyze or plot ngspice or xyce output data with Python
SystemRDL – generic compiler front-end for Accellera’s SystemRDL 2.0 Register Description Language.
Xschem – Schematic capture and netlisting: VHDL, Verilog, SPICE.
Xic – Schematic capture and IC layout editor.
XLS – XLS implements a High Level Synthesis (HLS) toolchain which produces synthesizable designs (Verilog and SystemVerilog) from flexible, high-level descriptions of functionality.
FPGA
CflexHDL – Design digital circuits in C, simulate really fast with a regular compiler. Flow from C -> Silice -> Verilog -> Migen/LiteX -> Bitstream
FOEDAG – Framework Open EDA Gui
fpga-bitstream – Generate a generica or fabric dependent bitstream
nextpnr – FPGA place and route
OpenFPGA – framework that enables rapid prototyping of customizable FPGA architectures
Raptor – commercial FPGA flow for FPGA design, RapidSilicon
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