EDA Open Source and Free Tools Wiki

Published by Daniel Payne on 04-21-2020 at 1:54 pm
Last updated on 05-29-2020 at 4:03 pm

SYSTEM

PandA-bambu – framework for research in high-level synthesis and HW/SW co-design
QElectroTech – Electronic diagrams
WaveDrom – draws your Timing Diagram or Waveform from simple textual description

PCB

Electric – IC design with schematic capture, layout, routing, LVS, PCB layout
Fritzing – Schematic capture and PCB layout
gEDA – Schematic capture
KiCad – PCB layout
KTechLab – Electronic and PIC microcontroller design
LibrePCB – PCB Layout
LTspice – SPICE simulation, schematic capture, waveform viewer, Analog Devices
PCB – PCB layout
pcb-rnd – PCB layout

IC

Alliance/Coriolis – VHDL compiler, simulator, logic synthesizer, automatic place and route
Chisel – Hardware compiler framework
cocotb – coroutine based co-simulation testbench environment for verifying VHDL and SystemVerilog using Python
Edalize – Python library for interfacing EDA tools (Icarus, Yosys, ModelSim, Vivado, Verilator, GHDL, Quartus)
FuseSoc – package manager and a set of build tools for HDL code.
GHDL – G HDL, a VHDL analyzer, compiler, simulator and synthesizer
Gnucap – GNU Circuit Analysis Package
Icarus Verilog – Verilog simulator (free)
ipyxact – Python based IP-XACT parser
IRSIM – switch-level simulator
LiteX – Migen/MiSoC based Core/SoC builder
Magic – IC layout, extraction, DRC
Migen – Python toolbox for HDL design
Netgen – Layout Versus Schematic (LVS) tool
nMigen – Python based HDL design
Ngspice – SPICE circuit simulation
OpenRAM – Memory compiler development framework
OpenROAD – RTL to GDS in 24 hours, no human in the loop
OpenSTA – Static Timing Analyzer
Oregano – schematic capture and SPICE circuit simulation
Qrouter – multi-level, over-the-cell maze router
Qucs – Quite Universal Circuit Simulator
RePlAce – global placement tool
SpinalHDL – HDL that creates VHDL or Verilog
Verilator – Verilog simulator
XCircuit – Schematic capture for SPICE netlists and PostScript
Xyce – Parallel analog circuit simulator from Sandia National Laboratories
Yosys – Verilog RTL synthesis

FPGA

Project IceStorm – Lattice bitstream format documentation
Qflow – digital synthesis flow using Verilog or VHDL, targets Xilinx or Altera
nextpnr – FPGA place and route
SymbiFlow – FPGA framework for tools, Verilog to bitstream

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