SILVACO 073125 Webinar 800x100
Semiconductor Expert Forum

Posted on

New TSMC 28nm Design Ecosystem!

New TSMC 28nm Design Ecosystem!
by Daniel Nenni on 05-28-2011 at 9:23 pm
Categories: EDA, Foundries, TSMC

TSMC rolled out the new reference flows for 28nm design as part of the Open Innovation Platform. The biggest surprise (to me) is that Cadence is STILL in the TSMC reference flows!

The updated TSMC OIP wiki is here, the Reference Flow 12.0 wiki can be found here, the AMS 2.0 reference flow wiki is here, and the official TSMC PR is here. The latest slides are included in the wikis for your viewing pleasure. TSMC customers can download the official materials at TSMC Online.

“TSMC customers can immediately take advantage of our 28nm advanced technology and manufacturing capacity while preparing for 20nm in the near future,” said Cliff Hou, TSMC Senior Director, Design and Technology Platform. “We have enabled customers to achieve their product design goals by closely collaborating with our EDA and IP partners to deliver a solid 28nm design ecosystem. In addition, the introduction of Reference Flow 12.0 and AMS Reference Flow 2.0 address critical design issues for the next generation of 28nm and 20nm applications.”

This announcement is a big fat hairy deal for several reasons:

[LIST=1]

  • Cadence is still partners with TSMC
  • 2.5D design
  • Emerging companies dominate
  • 28nm Power, Performance and DFM Design Enablement

    While Cadence executives pledge their allegiance to the open TSMC iPDK standard, Cadence product people continue to release INCOMPATIBLE products. The upcoming release of Virtuso GXL 6.1.5 (the high end version) will NOT allow a non SKILL based PDK to run (core dumps). My guess is that Virtuoso XL and L versions will soon follow. How will Cadence get away with this travesty? Big Cadence customers (80% of their revenue base) build their own PDK’s even if they use TSMC. Closed skill based PDK’s for Cadence customers versus open PDK’s for everyone else, great corporate strategy……. NOT! Cadence will be punished for this short sighted behavior by customers, it’s coming, believe it.

    TSMC will be the first fully 3D IC design capable foundry, no argument there. 2.5D design includes multiple dies to be integrated with a silicon interposer. Reference Flow 12.0 features new design capabilities in: floor planning, P&R, IR-drop, and thermal analysis to accommodate multiple nodes simultaneously. Also included is a new design for test methodology for 2.5D design.

    In addition to the “EDA Monopoly”, emerging companies continue to impregnate the TSMC reference flows:

    Apache, Arteris, AtopTech, Carbon Design System, CLK DA, Extreme DA, Sigrity, Sonics, SpringSoft, Berkeley DA, Ciranova, CST, EdXact SA, CWS, Helic, Integrand, Lorentz, and my personal favorite Solido DA. EDA innovation comes from emerging companies so TSMC is doing the semiconductor design ecosystem a big fat hairy favor here by putting new tools in silicon. NO OTHER FAB DOES THIS!

    Timing degradation from wire and via resistance, power leakage, hotspot checking and fixing are also addressed in the reference flows. Smaller geometries bring bigger problems, believe it.

    TSMC has a monster booth at DAC with a partner pavilion. The TSMC DAC page is herewith:

    In case you don’t follow my Twittering @DanielNenni: TSMC and UMC will be back at 95% utilization in Q3 due to surging orders from the mobile internet craze. Most of which include ARM processors @ 40nm bearing the names: Snapdragon for Qualcomm, Tegra2 for NVIDIA, Armada for Marvell, and i.MX for Freescale at TSMC and OMAP4 for Texas Instruments at UMC. TSMC also has 100+ tape-outs coming in at 28nm so don’t expect excess fab capacity anytime soon.

    Taiwan was absolutely crazy this month. The drought continues, the streets of Hsinchu were packed with scooters, and at2pmon Wednesday there was a bombing drill. For 30 minutes we were required to stay inside while the streets were cleared. This has been going on for years and it reminded me of elementary school where we hid from atomic bombs (cold war) under our desks.

    Don’t forget to share this on LinkedIn:

    • Posted on

    65nm to 45nm SerDes IP Migration Success Story

    65nm to 45nm SerDes IP Migration Success Story
    by Daniel Nenni on 05-25-2011 at 3:43 pm
    Categories: Uncategorized
    4 Comments

    The problem:To move a single lane variable data rate SerDes (serializer-deserializer) from a 65nm process to a 45nm process, achieving a maximum performance of up to 10.3 Gbps. This is a large piece of complex mixed-signal IP with handcrafted analog circuits. Circuit performance and robustness are critical and must be maintained in the migrated implementation.

    The original design consisted of over 30 blocks with a hierarchical device count of around 30,000 (about 200,000 flat).

    After the first migration, business opportunities arose requiring the same SerDes IP to be moved to two further different 40nm processes.

    Design Environment: 65nm Serdes has been designed in Cadence Virtuoso XL, using the 65nm foundry provided PDK (technology files, pcells, etc). Target 45nm migrated result should be restored into a Cadence Virtuoso XL database environment using the new target 45nm foundry provided PDK. All the Cadence database specific object need to be maintained (pcells, via cells, connectivity, etc.)

    The main changes : There were many changes in design rules between the two processes: Dummy poly insertion and pitching being the most challenging. In addition, all devices were resized and the new sizes needed to be gathered from the netlist (netlist-driven migration).

    A layout clip showing devices after automatic dummy poly insertion and gate gridding (enforcing strict poly pitch)

    The main requirements:

    • · The basic topology needed to be preserved.
    • · The design hierarchy needed to be preserved.
    • · Matching devices and routing should remain as such. Other topology sensitive features such as symmetry, alignment, etc, should be maintained.
    • · The migrated SerDes should be LVS clean. This includes both connectivity as well as matching the new schematic device sizes.
    • · The flow should allow quick sizing and ECO iterations
    • · The migrated SerDes should have minimal remaining DRC violations requiring manual fixup.
    • · Maintain data integrity: Virtuoso data structure and all objects kept intact

    The schedule: The productivity goal was set to at most 1/5 of original layout time. (minimum 80% effort and time savings) .

    Quick Initial Prototyping: One of the first goals was to figure out the effective scaling factor of the migrated IP. This is one of the clear benefits of automated migration which allows designers to try multiple scaling and sizing scenarios based on the target technology devices and rules. Many experiments can be done quickly and very early on, to figure out the effective scaling, footprint, effect on performance, and other consequences of each scaling and sizing scenario.

    How the migration was addressed: The entire Serdes IP comprises over 30 main blocks, each having up to 10 level of hierarchy and an average of 1000 devices (hierarchical count).To facilitate concurrent layout-circuit optimizations with quick turn-around time, a block-by-block execution method was chosen.While performing each block at a time, the migration flow also takes care of global (top) level metals and over-the-block supply rails to make sure that the blocks are properly positioned and connected within the top level. Most of the blocks are custom handcrafted using device level programmable cells (Pcells) of the original 65nm foundry PDK . These Pcells as well as other symbolic structures had to be mapped to and substituted by similar devices and structures from the target foundry 45nm process. The migration software uses this mapping to generate the new devices and objects using the right parameters, make room for each of their instances, place them and connect them in the migrated layout. A few blocks also used digital control sections that were implemented using a specific logic cell library shared among all the blocks. This common logic cell library was also migrated to the 45nm target process rules and maintained as a common library across the entire IP, and then used during the block-level migration.

    Device Sizing     : Final sizing for devices was not fully determined before starting the project. Initial sizing was done based on schematics and then was subsequently refined after layout extraction and circuit validation. This is where having an automated migration flow makes a huge difference as once the flow is in place, all subsequent sizing and tuning layout iteration are run very quickly ( in less than an hour). Using this block-by-block approach enabled having a virtual “assembly line” pipeline of blocks in different stages of migration and tuning and accelerated the overall project significantly.

    Results: The SerDes migration was delivered on-time. LVS was virtually clean (there were a few minor issues due to incompatibilities between the PDK libraries). DRC quality was better than expected, with most blocks having under 50 DRC violations left. In fact the project exceeded its initial productivity goals: each block takes only minutes to run, and the last few remaining DRC errors took only a few hours to clean up. The overall effort, including the manual layout cleanup, took less than 1/10 of the original layout time (90% effort and time savings).
    Automatic migration preserves symmetry and matching. Same clip before and after migration.

    65nm (green) versus 45nm (purple)

    Why Sagantec:The IP design team looked at different commercial solutions for Analog/MS migration and evaluated a few alternative offerings from multiple EDA vendors. While other vendors addressed some aspects of the problem, the customer found Sagantec as having the most complete solution and one that most effectively addresses the size, complexity and the overall layout effort productivity goals. Another significant factor was supporting and maintaining the Cadence Virtuoso database and objects which was important to the design team. Overall the Sagantec approach seemed the most practical and least disruptive to the team’s current design flow and tools.

    Consecutive Successes:     Following the success of this migration project, the IP design team decided to use the same flow to migrate this IP to two other 40nm processes (using different PDKs and technology files respectively). Each of these subsequent process migrations was also a success, completed on-schedule and exhibited similar productivity gains. Overall this migration methodology and flow enabled the team to respond quickly to new business opportunities and process requirements, leveraging their original design investment and minimizing their efforts per each process implementation.

    Custom IP migration: Moving a complex custom IP block from one process to a different process can either be done by an experienced layout team or using an automated flow that handles almost all of the work automatically, such as Sagantec’s migration technology. For migration to older process nodes or between similar processes, it is possible that a shrink followed by manual fix-up of violations would work, but in advanced process nodes and when the processes have very different rules, the number of violations generated can be overwhelming and impractical for such approach. The alternative would be a complete redesign, which in this case would be prohibitively expensive in both schedule and resources required. In addition to licensing migration software, Sagantec has also experienced application engineers that can do migrations as a service to minimize turn-around time, get the highest quality results and maximize ROI.

    Sagantec Demo Suite Registration

    Note: To read/write comments you must be logged in

    Posted on

    3D IC @ #48DAC

    3D IC @ #48DAC
    by Daniel Nenni on 05-23-2011 at 4:54 pm
    Categories: EDA, Events

    A three-dimensional integrated circuit (3D IC ) is a chip in which two or more layers of active electronic components are integrated both vertically and horizontally into a single circuit. The semiconductor industry is hotly pursuing this emerging technology in many different forms, as a result the full definition is still somewhat fluid.

    If you need to increase your system- and/or IC designs’ performance, while reducing power dissipation, space required and eventually cut NRE and unit cost, you want to update yourself at #48DAC on our industry’s progress regarding 3D ICs.

    3D Tour Guide for DAC 2011:
    To assist you in this effort, the GSA’s 3D IC Working Group compiled this year again the “Tour Guide to 3D-IC Design Tools and Services”. It includes 3D-centric information from 14 EDA vendors, 4 R&D centers and industry organizations, 3 market research firm and 1 value chain provider. This 3D Tour Guide can be downloaded here:

    If you want to know more about the 3D IC Working Group’s activities, you can download presentations given by 3D experts at recent meetings here:

    3D-focused DAC Event:
    On Monday morning, June 6, Herb Reiter will moderate a pavilion panel on the exhibit floor (Booth 3421) with the title : “3D IC: Myth or Miracle?”

    Riko Radojcic from Qualcomm, Ivo Bolsens from Xilinx and Suk Lee from TSMC will outline their view of 3D technology and answer questions from the audience.
    More about this panel here:

    At the end of this 3D panel the GSA will offer you – in exchange for your business card – a hard copy of the 3D Tour Guide with its 60+ pages of 3D information.

    Please join us on Monday morning, 10.30 am at Booth 3421. Utilize the 3D Tour Guide to direct you to Tools and Services for 3D IC design and manufacturing.

    Other 3D-focused events BEFORE the summer break:
    June 29 to July 1will be the “Design for 3D” conference in Grenoble, France.
    More about agenda, registration here.

    In addition to the IC-design focused events about, our industry’s manufacturing experts are also going to address 3D Technology in several workshops and on the exhibit floor at the upcoming Semicon West in San Francisco, from July 12 to 14. More here:

    If you want to join the GSA 3D IC Working Group and contribute to general 3D topics or specific efforts (3D test, data exchange formats, 2.5D, …) please contact Herb Reiter with a brief outline of your strengths and the topics you want to influence.

    Herb Reiter
    Chair of the GSA 3D IC Working Group
    herb@eda2asic.com

    Posted on

    48th Annual Design Automation Conference

    48th Annual Design Automation Conference
    by Daniel Nenni on 05-23-2011 at 8:08 am
    Categories: EDA, Events

    The 48[SUP]th[/SUP] Design Automation Conference (DAC) is now upon us. DAC is billed as “the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions” for which I would have to agree with 100%.

    The first DAC I attended was in 1984, Albuquerque New Mexico, which was one of the first to allow exhibitors. It was an exciting time in semiconductor design, so much innovation, new technology everywhere, the Design Automation Conference is and has always been the cornerstone of EDA. This will be my 28[SUP]th[/SUP] DAC and certainly not my last since the Rapture didn’t get me, unless of course the world ends on October 21st.

    SemiWiki will be at DAC giving away iPad2s in booth #1432.Register for SemiWiki on an iPad2 at the booth and you qualify to win. Current SemiWiki members just check in and qualify to win.


    This year I was part of the DAC planning process and organized two pavilion panels which is what this blog is really about:

    The first panel is Hogan’s Heroes: The Reaggregation of Ecosystem Value

    Topic Area: Business
    Tuesday, June 7, 2011
    Time:11:00 AM—12:00 PM
    Location:Booth #3421

    Summary:The semiconductor ecosystem shifts its value aggregation on somewhat predictable cycles. These are followed by longer periods of stability during which new companies are created. The latest cycle is being driven by system houses. What impact will these new trends in system design have on EDA and IP business models and enterprise value?

    Organizer:Daniel Nenni – SemiWiki, Danville, CA
    Moderator:Jim Hogan – Tela Innovation, Inc.,Campbell,CA
    Speakers:Ajoy K. Bose – Atrenta, Inc., San Jose, CA Jack Harding – eSilicon Corp., Sunnyvale, CA Grant A. Pierce – Sonics, Inc., Milpitas, CA

    The second panel isWhy the Delay in Analog PDK?

    Topic Area:     Analog/Mixed-Signal/RF Design
    Wednesday, June 8, 2011
    Time:10:30 AM — 11:15 AM
    Location:Booth #3421

    Organizer:     Daniel Nenni – SemiWiki, Danville, CA
    Moderator:Steven Klass – SMSC,Phoenix,AZ
    Speakers:Mass Sivilotti – Tanner EDA, Monrovia, CA, Tom Quan – Taiwan Semiconductor Manufacturing Co., Ltd., San Jose, CA Ofer Tamir – TowerJazz, Newport Beach, CA

    Summary:    Why does it take so long for foundries to release analog/mixed-signal process design kits (PDKs)? The amount of AMS content in your designs is growing, and the pressure to move to smaller process nodes is increasing. This is your chance to talk to the people who develop your PDKs and reference flows!

    Tom is a natural in front of the camera, he did it in one take! This is must see TV!

    As for me, if we haven’t met please introduce yourself and feel free to buy me a drink. If we already know each other just buy me a drink. This DAC I will be blogging for beverages! Don’t forget to click the LinkedIn share button below in support of the 48th Design Automation Conference. See you in San Diego!


    *Note: to read/write comments you must log in.

    Posted on

    FPGA Prototypes Made Easy

    FPGA Prototypes Made Easy
    by Paul McLellan on 05-23-2011 at 5:00 am
    Categories: Uncategorized
    2 Comments

    FPGA-based prototype boards are a fast, cost-effective platform for SoC system validation but they are notoriously difficult to set up and to debug. There is a big upside, however, allowing early software integration and testing and thus finding bugs in both the software and the SoC earlier. This approach is much cheaper than commercial emulators. However, problems of debug visibility and the need for repeated slow FPGA compiles limits their use to late in the design cycle.

    The basic problem is that you need to decide in advance which signals to monitor, and add code to the RTL to bring those signals out. Of course, they always turn out to be the wrong set of signals, but to make a change requires adding the new signals and recompiling the whole FPGA. The number of pins available also restricts how many signals can be probed.

    What you would really like is to be able to have thousands of signals probed, and be able to change your mind to add new probes without requiring a complete recompile of the FPGA which can take hours.


    Protolink proble visualizer is a mixture of hardware and some clever software that gives just this capability. The way it works is that the RTL for the design is augmented with a bit of code before compilation (there is an overhead of a few percent for this). After compilation, the detailed routing of the FPGA is analyzed, the dummy module is replaced with the actual gates required for Protolink and then the verification can be run with the ProtoLink interface card attached to the prototype board. If an additional signal needs to be probed then small adjustments to the FPGA are all that are required.

    The traditional approach gives the capability to monitor tens of signals for a limited number of cycles, and with the time required to add a new signal measured in hours or even days. With Prove Visuallizer it is possible to monitor thousands of signals for millions of cycles, and adding a new signal to probe is a matter of minutes.

    The whole system is interfaced through Verdi, giving a common user-interface for simulation, FPGA prototyping and conventional in-circuit emulation. Verdi’s advanced visualization, tracing and analysis all operate to produce an extremely productive test and debug environment.

    Probe Visuallizer backgrounder

    Posted on

    Analyzing and Planning Electro-static Discharge (ESD) Protection

    Analyzing and Planning Electro-static Discharge (ESD) Protection
    by Paul McLellan on 05-23-2011 at 5:00 am
    Categories: Ansys, Inc., EDA

    ESD has historically been a big problem analyzed with ad-hoc approaches. As explained earlier, this is no longer an adequate way to plan nor signoff ESD protection.

    Pathfinder is the first full-chip comprehensive ESD planning and verification solution. It is targeted to address limitations in today’s methodologies. Using a full-chip modeling approach, it can verify that a design meets ESD guidelines and identify vulnerable areas of the design. It can report if current density exceeds limits for wires and vias. It works for both digital and analog circuits.

    There are three different types of analysis.

    [LIST=1]

  • First, human body model (HBM) and machine model (MM) checks. These are the ESD problems that can result from either humans touching the pins or during manufacturing test and assembly. Pathfinder will check to ensure than if ESD voltage occurs between any two pins (or bumps) then it will traverse one or more clamp cells placed between those pins. First the loop resistance through each clamp cell is estimated. If the resistance is too high then that clamp cell is ignored and only any remaining cells (if any) for that path are considered. Checks are performed to ensure that the ESD protection is sufficient between each pair of pins.
  • Charged device model (CDM) checks. This is check for build up in logic, package capacitors and other circuits such as memories that need to have low resistance discharge paths.
  • Current density checks. This involve estimating the current density in wires following the injection of current into any pin pair. It calculates the current through the wires and vias and highlights any which fail the current density limits (as defined by the process guidelines).

    Following this analysis, extensive information can be created to enable debugging: reports, histograms and graphical displays overlaid onto the layout. This makes it easy to perform what-if experiments without leaving the tool. Once any changes are confirmed, an ECO report is created to allow for implementation of those changes in the final layout of the chip.

    Pathfinder is used in two different ways. Early in the design it can be used for ESD planning, especially on bumped chips which need to contain extensive ESD protection circuitry in the core and not just in an IO ring. If this is not done, and ESD protection circuitry is only added very late in the design process, it risks causing unexpected area (and perhaps timing) problems and thus potentially major schedule impact. The second way is to analyze the final design to signoff on the ESD protection prior to tapeout.

    Pathfinder white paper

    • Posted on

    Right-source your electronic designs

    Right-source your electronic designs
    by nitindeo on 05-19-2011 at 5:42 pm
    Categories: Uncategorized

    Concept2Silicon Systems (C2SiS) is focused on providing complete solutions for complex SoC and System designs with best in class engineering capabilities and most cost-efficient business model. Our highly capable engineering team has experience in delivering 200+ silicon and system design solutions to its customers in the most advanced semiconductor process technology nodes up to 28nm.


    We have delivered extremely tough design criteria for embedded ARM with low-power and high-performance on a tight timeline. Our customers include ARM, TI, Cypress and the large communications company in Southern California. Please go to www.concept2silicon.com for more information.



    Posted on

    Cadence Virtuoso 6.1.5 and ClioSoft Hardware Configuration Management – Webinar Review

    Cadence Virtuoso 6.1.5 and ClioSoft Hardware Configuration Management – Webinar Review
    by Daniel Payne on 05-19-2011 at 5:33 pm
    Categories: Cadence, Cliosoft, EDA

    Introduction
    Cadence and ClioSoft made a webinar recently and I’ll summarize what I learned from it.

    What’s New from Cadence in Virtuoso 6.1.5

    • Back2Basics (28nm rule integration, Skill improved with object-oriented, OASIS support, HTML Publisher, Waveform re-written for better Analog support, smaller Waveform db files, generate layout from schematic source improved )
    • Connectivity Design (smarter wire to via automation, better auto routing for bus and diff pair, one router simplifies setup time, low power using Common Power Format with visual spreadsheet)
    • Design Constraints (in schematic add layout constraints for Encounter, constraint checking simplified, constraints are bi-direction schematic-layout)
    • Selective Automation (reliability analysis integrated, fluid guard rings without tweaking Pcell code )
    • Parasitic Aware Design (how does physical layout affect performance, schematic-> constraints-> tests and sims -> pre-layout parasitic estimates -> circuit optimization -> MODGEN creation -> device placement -> net routing -> in-design verification -> extraction -> parasitic comparison)

    Do Not

    • Use 6.1 like you did 5.1, there’s no benefit

    Do

    • Take advantage of new features to get benefits

    ClioSoft
    Karim Khalfan talked about the SOS tool used by IC designers:

    • Hardware Configuration Management – should be easy to use
    • Design Management is for the entire IC team
    • Manage everything: Spec, RTL, Verification, P&R, Analog, Custom Layout
      • Large teams, multiple sites, data explosion, binary files, complex flows, IP and re-use, design variants
    • Features
      • Version control – text and binary files, folders, tags and labels
      • Release management – take snapshots
      • Issue tracking – connect to your favorite tools
      • Design reuse – reference previous projects
      • Global Collaboration – client/server architecture, cache, synched
      • Authentication – users identified, groups (schematics, layout, etc.)
      • Design Aware Integration – integrated into Virtuoso
    • Hardware Design
      • Easy to checkin and checkout, use design objects
      • Disk use is optimized, not sending terabytes across network
      • Isolated and shared work spaces, you decide
      • Design hierarchy can be managed
      • Visual differences – compare schematics or layouts, click on each change
      • Integration directly into Virtuoso
    • DDM is built just for IC designs, no 3rd party SW needed

    Then Karim did a live demo of Virtuoso 6.1.5 with ClioSoft menus (Design Manager) and commands explained as he went through the process of checking in cells and checking out cells for an IC project. Used both the Library Manager and Schematic tools in Virtuoso. Visual Difference shown between two versions of a schematic or layout, flat or hierarchical.

     

    Summary
    Cadence and ClioSoft have really created a powerful and flexible IC design environment for team-based design. Both the designers of schematics and the layout people will benefit from using hardware configuration management by keeping track of their complex projects all within the familiar Virtuoso tools.

    Also Read

    How Avnera uses Hardware Configuration Management with Virtuoso IC Tools

    Hardware Configuration Management and why it’s different than Software Configuration Management

    Webinar: Beyond the Basics of IP-based Digital Design Management

    Posted on

    A New Hierarchical 3D Field Solver

    A New Hierarchical 3D Field Solver
    by Daniel Payne on 05-19-2011 at 2:04 pm
    Categories: EDA

    Introduction
    3D field solvers produce the most accurate netlists of RC values of your IC layout that can then be used in SPICE circuit simulators however most of these solvers produce a flat netlist which tends to simulate rather slowly. Thankfully several years ago the first hierarchical SPICE tools were offered by Nassda (HSIM) and Cadence (UltraSim) but they require a hierarchical netlist to simulate large designs quickly and efficiently.

    What’s New?
    This week I spoke with Dermott Lynch of Silicon Frontline about their latest Hierarchical 3D Field Solver named H3D.

    Q: What is hierarchical extraction a big deal?
    A: Most SOCs have many memory and other repeated structures in their layout, so exploiting layout hierarchy provides a big benefit to users.

    Q: What kind of approach did you use with H3D to create a hierarchical netlist?
    A: We have a patented approach based on the Random Walk Algorithm, interested readers can see the patent here.

    Q: How are the CPU run times with your hierarchical approach to extraction?
    A: This new tool shows a sub-linear increase based on the number of nets.

    Q: Does H3D fit into my existing IC tool flow?
    A: Yes, it reads a standard layout and produces a netlist that can be: distributed, lumped, C, R, RC and RCCc.

    Q: How about using distributed CPUs?
    A: We support both distributed and multi-core CPUs to help speed up the results.

    Q: Compared to a flat extractor, what kind of speed improvements should I expect with this hierarchical extractor?
    A: From 10X to 100X speed improvements, based upon how much hierarchy there is in your layout. Designs with the most hierarchy are: FPGA, Image Sensors and memory rich SOCs.

    Q: Should I expect the RC numbers extracted from your flat tool to match the hierarchical tool?
    A: Yes, they are statistically equivalent values.

    Q: How does H3D help my post-layout simulation run times?
    A: We’re seeing speed improvements between 2X and 7X faster using the H3D netlist in a Fast SPICE simulator.

    Q: How popular are your field solver tools?
    A: Over 350 designs have been verified at over 30 customers, and they’ve been adopted by 12 of the top 30 semiconductor vendors.

    Q: What is pricing like for H3D?
    A: Pricing starts at $99K annually and there are several configurations to choose from.

    Summary
    If your IC design requires the highest accuracy for parasitic RC values and the layout has hierarchy then you should start to consider the tool flow of H3D for hierarchical extraction followed by a Fast SPICE tool like HSIM or UltraSim.

    *Note: to read/write comments you must log in.

    Posted on

    Electro-static Discharge (ESD)

    Electro-static Discharge (ESD)
    by Paul McLellan on 05-18-2011 at 4:26 pm
    Categories: Ansys, Inc., EDA

    Electro-static discharge (ESD) has been a problem since the beginning of IC production. Chips function on power supplies of up to a few volts (depending on the era) whereas ESD voltages are measured in the thousands of volts. When you reach out for your car door handle and a spark jumps across, that is ESD. If you were touching a chip instead of your car (and cars contain plenty of chips these days) then the chip has to be able to absorb those thousands of volts and harmlessly dump them without letting voltages or currents on the chip go beyond what can be handled. ESD doesn’t just cause a potential problem when it happens, it can physically destroy the chip. Estimates are that as many as 35% of all in-field chip failures are due to ESD.

    For example, if ESD is incorrectly handled and very high voltages end up on the gate of the chip, the discharge can destroy the thin oxide underneath the gate and make that transistor, and probably thus the whole chip, inoperable. Since the thin oxide is getting thinner with each process node it is not surprising that ESD is a problem that is only going to continue to get worse. Metal geometries are also getting smaller, and so have a reduced capacity to handle a current surcharge.

    There are other reasons that it is getting worse, not just shrinking geometries. The higher levels of integration on mixed signal chips man that there are many isolated independent power/ground networks, which aggravates the problem. Also, there are more and more hand-held devices (cell-phones etc) which means that there is more direct access to the ICs. You are not very likely to have n ESD problem with the engine-controller in your car since you don’t touch it. The base of your iPhone has a socket with lots of connectors that go straight to the chips inside the phone.

    ESD events can also occur during packaging, assembly and test of the IC. And, in fact, charge buildup inside the chip can also cause ESD failures, especially from in-package capacitors and from on-chip memories.

    ESD protection has typically been implemented by placing clamp circuits at appropriate locations on the chip that do two things. First, provide a low impedance discharge path for the ESD and second, clamp the signal voltage at a level that avoids dielectric breakdown. Historically these clamp circuits have been placed in the I/O and power/ground pads. Input pads are especially vulnerable since the input pin has to be connected to the gate of the input driver. The clamp circuits are quite large but since the pads and their drivers are already large this doesn’t have a huge impact.

    However, modern designs often have c4 bumps all across the chip, and with the coming of 3D (and 2.5D) designs this will only increase. This means that clamp circuits, which are large, are needed in the core of chip too and thus compete for area with circuitry in the core such as standard cells.

    Historically, analysis of ESD has been done in a fairly ad hoc manner, with design guidelines and manual verification. But as the complexity of the design and the number of power/ground nets increases this is no longer adequate. A full-chip ESD verification solution for ESD signoff is required. Indeed, as more ESD protection is needed in the core, it is no longer enough to analyze after the design is complete, ESD protection needs to be planned since it has potentially large impact on the area available in the core for actual implementation of the design.

    Whitepaper on Pathfinder

    * Note you must be logged in to read/write comments