TSMC rolled out the new reference flows for 28nm design as part of the Open Innovation Platform. The biggest surprise (to me) is that Cadence is STILL in the TSMC reference flows!
The updated TSMC OIP wiki is here, the Reference Flow 12.0 wiki can be found here, the AMS 2.0 reference flow wiki is here, and the official TSMC PR is here. The latest slides are included in the wikis for your viewing pleasure. TSMC customers can download the official materials at TSMC Online.
“TSMC customers can immediately take advantage of our 28nm advanced technology and manufacturing capacity while preparing for 20nm in the near future,” said Cliff Hou, TSMC Senior Director, Design and Technology Platform. “We have enabled customers to achieve their product design goals by closely collaborating with our EDA and IP partners to deliver a solid 28nm design ecosystem. In addition, the introduction of Reference Flow 12.0 and AMS Reference Flow 2.0 address critical design issues for the next generation of 28nm and 20nm applications.”
This announcement is a big fat hairy deal for several reasons:
While Cadence executives pledge their allegiance to the open TSMC iPDK standard, Cadence product people continue to release INCOMPATIBLE products. The upcoming release of Virtuso GXL 6.1.5 (the high end version) will NOT allow a non SKILL based PDK to run (core dumps). My guess is that Virtuoso XL and L versions will soon follow. How will Cadence get away with this travesty? Big Cadence customers (80% of their revenue base) build their own PDK’s even if they use TSMC. Closed skill based PDK’s for Cadence customers versus open PDK’s for everyone else, great corporate strategy……. NOT! Cadence will be punished for this short sighted behavior by customers, it’s coming, believe it.
TSMC will be the first fully 3D IC design capable foundry, no argument there. 2.5D design includes multiple dies to be integrated with a silicon interposer. Reference Flow 12.0 features new design capabilities in: floor planning, P&R, IR-drop, and thermal analysis to accommodate multiple nodes simultaneously. Also included is a new design for test methodology for 2.5D design.
In addition to the “EDA Monopoly”, emerging companies continue to impregnate the TSMC reference flows:
Apache, Arteris, AtopTech, Carbon Design System, CLK DA, Extreme DA, Sigrity, Sonics, SpringSoft, Berkeley DA, Ciranova, CST, EdXact SA, CWS, Helic, Integrand, Lorentz, and my personal favorite Solido DA. EDA innovation comes from emerging companies so TSMC is doing the semiconductor design ecosystem a big fat hairy favor here by putting new tools in silicon. NO OTHER FAB DOES THIS!
Timing degradation from wire and via resistance, power leakage, hotspot checking and fixing are also addressed in the reference flows. Smaller geometries bring bigger problems, believe it.
TSMC has a monster booth at DAC with a partner pavilion. The TSMC DAC page is herewith:
In case you don’t follow my Twittering @DanielNenni: TSMC and UMC will be back at 95% utilization in Q3 due to surging orders from the mobile internet craze. Most of which include ARM processors @ 40nm bearing the names: Snapdragon for Qualcomm, Tegra2 for NVIDIA, Armada for Marvell, and i.MX for Freescale at TSMC and OMAP4 for Texas Instruments at UMC. TSMC also has 100+ tape-outs coming in at 28nm so don’t expect excess fab capacity anytime soon.
Taiwan was absolutely crazy this month. The drought continues, the streets of Hsinchu were packed with scooters, and at2pmon Wednesday there was a bombing drill. For 30 minutes we were required to stay inside while the streets were cleared. This has been going on for years and it reminded me of elementary school where we hid from atomic bombs (cold war) under our desks.
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