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Berkeley Design Automation at DAC

Berkeley Design Automation at DAC
by Daniel Payne on 06-17-2011 at 4:01 pm
Categories: Uncategorized

Intro
Simon Young, Product Marketing manager at BDA gave me an update at DAC last week on their circuit simulator, Analog Fast SPICE (AFS).

Notes

Quarterly release: 2011 Q2 now

Speed Improvements: Still 5 to 10X speed improvement over other SPICE tools

Multi-Threading – 2 to 4 X improvement using 4 to 8 cores.

Device Noise – three ways to compute noise: Transient, PSS/pnoise, Oscillator
– Comparing transient noise with PSS they agree with each one to one (Cannot do that in Spectre, they are different values)

Customers – About 120 logos this year

Distributors – Canada, India and Israel added in past year

Competitors – Spectre, FineSIM, Eldo, HSPICE

Customers – high speed IO design, , PLL/DLL clock synthesis and recovery, data convertors, delta-sigma modulators, full-circuit RFCMOS ICs, memories.

Capacity – 10M elements

Summary
BDA coined the product category Analog Fast SPICE to denote a circuit simulator that is SPICE accurate with a 5X to 10X speed improvement over traditional SPICE algorithms. The other EDA vendors claim to have caught up to BDA’s tool, however you’ll just have to benchmark it on your own circuits to determine the speed, accuracy and capacity claims.

I continue to see BDA in growth mode by adding new staff, so their products must be selling well around the world.

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GlobalFoundries Production-Ready @ 28nm in Multiple Locations!

GlobalFoundries Production-Ready @ 28nm in Multiple Locations!
by Daniel Nenni on 06-15-2011 at 11:02 am
Categories: Foundries, GlobalFoundries

GLOBALFOUNDRIES showed off its 28nm design ecosystem at #48DAC last week in San Diego. The company featured a full design ecosystem for its 28nm High-k Metal Gate (HKMG) technology, including silicon-validated flows, process design kits (PDKs), design-for-manufacturing (DFM), and intellectual property (IP) in partnership with industry leaders. 28nm is the second node of HKMG production for GFI with 32nm AMD Llano dice already in the field. CPU’s and GPU’s are the most difficult designs to manufacture and Llano is both.

In case you missed it, here is a reprint of a 28nm HKMG overview from GFI just prior to #48DAC:

High-K/Metal Gate (HKMG) is one of the most significant innovations in CMOS fabrication since the development of silicon VLSI. The 28nm technology is designed for the next generation of mobile smart devices demanding faster GHz processing speeds, lower standby power and longer battery life. To meet these demands, the 32/28nm HKMG solution is a “Gate-First” approach that shares the process flow, design flexibility, design elements and benefits of all previous nodes based upon poly SiON gates. This solution is far superior to present alternatives in scalability (performance, power, die size, design compatibility), cost (a typical foundry customer will save tens of millions of dollars over the course of a 28nm vs. 40nm product portfolio lifecycle) and manufacturability

GLOBALFOUNDRIES’ 28nm-SLP technology is the low-power CMOS offering delivered on a bulk-silicon substrate for mobile applications. Relative to other 28nm technologies, it achieves its lower cost platform by substantially reducing process complexity and mask counts. It offers design flexibility with multi-channel length capability and the ultimate in small die size. Available options include multiple SRAM bit cells for high density and high performance.

Since this process downsizes the footprint and power utilization, it optimizes energy efficiency, which translates into significantly longer battery run times and fewer recharge cycles; the benchmark of wireless devices moving forward. The gate-first HKMG process utilizes a functional voltage below 0.8V, scaling 28nm performance and power proportionately against 40nm-LP poly SiON. Overall performance gains include a 49% higher frequency capability, a 44% reduction in energy utilization per switch and >25% reduction in leakage power per circuit (see Figure 1). The 28nm- SLP, Gate-First process also supports standard overdrive practices providing additional performance and flexibility gains for a broader application base (wireless AND wired).

A significant benefit of 28nm-SLP technology is that it provides hefty analog “headroom” (Vcc-Vt) and low noise performance relative to the offerings of other foundries. Gate-First enables a reduction in design complexity by preserving design architecture and layout style, thereby leveraging design investments with IP reuse. This design compatibility helps reduce the overall risks of adopting 28nm.

The Super-Low Vt option provides a performance boost over traditional Vts at a given process node, opening the door for greater than 2GHz performance. The resulting performance boost with a minimal increase in power makes this option attractive to applications with specific thermal requirements that still require the largest performance envelope.

Conclusions
The 28nm low-power technology presents tremendous value over the 40nm process, for the industry. It achieves substantially smaller die size than competing foundry offerings. Reduced risk is a hallmark of this low-power technology. It facilitates proven high-volume manufacturing at multiple Common Platform Alliance locations globally as well as a fully enabled design ecosystem with IP and tools and proven design flows, while sustaining the industry design style, flexibility and infrastructure utilized at 40nm and all previous technology nodes. This available technology provides superior performance and analog headroom for wider design margin and lower manufacturing cost.

The GFI Concurrent Newsletter is HERE.

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Synopsys IC Validator at DAC

Synopsys IC Validator at DAC
by Daniel Payne on 06-14-2011 at 3:14 pm
Categories: EDA, Synopsys

Intro
At DAC last week I visited the Synopsys demo suite to see what’s new with IC Validator.


Notes
Stelios Diamantidis, PMM
– In-design physical verification
– Sign-off reveals thousands of late stage DRC violations
– 28nm has 1.5K rules, 15K runset sizes
– Metal Fill changes timing
– The DRM can be changed throughout the life of the process

Timing Closure – can be too slow, too many iterations, too time consuming
– A new methodology is needed

IC Validator – verify as you go, early, not at the end of routing
– Run during: Floorplan, P/G, Placement, CTS, final route

In-Design PV: Metal Fill
– Foundry runset used by IC Compiler
– Evaluate timing of critical nets, timing aware metal fill
– Automate ECO process, identify shorts, push route out, comply to DRC rules
– Example of timing driven metal fill evaluation
o Renesas: 6X faster TAT using ICV with ICC
o AMD: 30 minutes to complete Metal Fill, 580K nets

In-Design PV: Signoff DRC
– Incremental Checking (analysis by Layer, Area or rule)
– GDS Merge – remove cell boundaries (full mask checking on demand)
– Automatic DRC Repair (highly localized, router driven), router told where to correct violations
– ST: Used the flow to find and fix 340 violations in just 35 minutes
– TI: Up to 100% auto fix rate , Automatic DRC Repair (ADR)

Smart Error Management
– Milkyway Intgration (direct access to properties)
– Error categorization (automatic linking of violations)
– Interactive filtering (querying or sorting of violations)

Chris Grossman – Corporate AE
Demo of IC Validator, live
– Start with IC Compiler, DRC checking shows 20,330 violations
– Stepping through each DRC violation graphically, decide how to fix DRV violations with scripting or manual efforts
– Another way is to use ICV (DRC checking) inside of ICC (P&R)
– Results of DRC checking shows only 3926 violations, not 20,330 at the end of detailed P&R
o Filter the DRC violations: P/G Nets, Clock Nets, Signal Routes, User Routes
o Re-run just one rule at a time, re-run rules in one rectangular area at a time
o You can leave the floorplanning stage knowing that you are DRC clean
o After checking DRC after PG, it’s time to run DRC after Clock Tree Synthesis (CTS)
o Now only 16 DRC violations found (Found a RAM placement too close to a VDD)
o Run MergeGDS to see where this RAM instance has a DRC violation
o After CTS time to run detailed routing, found only 143 DRC violations now

Summary
– Run In-Design PV at each stage of physical design, not at the end of detailed routing
– In-design physical verification saves weeks of time over the old implement then verify approach
– IC Validator: pre-routing checks, routing checking, automatic repair, timing aware repair
o Next release: 1.5X faster DRC runs, 1.5X smaller fill size, 3X less fill memory
o 20nm: double patterning required, native DPT coloring engine, In-Design decomposition checking
o Equation-based DRC
o Debug Productivity: will have a new LVS graphical schematic viewer, LVS equivalent error browser, graphical runset debugger
o Advanced Nodes: fill-to-target (correct by construction), pattern matching (Prevents manufacturing limiting layout patterns)

ICC – Has 60% market share in P&R

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Extreme DA at DAC

Extreme DA at DAC
by Daniel Payne on 06-14-2011 at 3:01 pm
Categories: Uncategorized

Intro
Over the lunch hour on Tuesday at DAC I met with Emre Tuncer, VP – Product Engineering & Applications and heard about extraction and timing analysis.

Notes

GoldX – parasitic extractor. Fast extractor, recently announced, all new technology, early customer adoption. One customer deploying it in 40nm, soon to be 28nm.
– Sold stand alone.
– Fast run times.
– Scalability, more cores better speed.
– Within 2% of a 3D field solvers on average. Mean is 1.5%, sigma is 1%.
– SPF timing differences are within 5ps.
– Cell-based extractor (not transistor level tool, stay tuned for device extraction)
– Extract each block, then stitch SPF files together at the top level
Focus –static timing analysis (Engine is statistical), reduce the turn around time, less pessimistic models (less fixing).
TSMC – Gold Time is endorsed for Reference Flow (Statistical Timer).
Prime Time, why switch ?
– Faster turn around time
– As good or better than SPICE accuracy
– Better reductions than Prime Time, reduce the amount of pessimism

Gold Time – out for awhile now, OCV is important and short turn around times
– Broadcomm
– Qualcomm
– Xilinx
– Not working as closely with Common Platform partners yet, mostly TSMC
– Quick run times using efficiency, MT

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Tanner EDA at DAC

Tanner EDA at DAC
by Daniel Payne on 06-14-2011 at 2:40 pm
Categories: EDA, Tanner EDA

Intro
For 22 years now Tanner EDAhas been in the business pf offering tools for AMS and MEMS designers. I learned what’s new at DAC on Tuesday morning.

Notes
Nicholas Williams – Director of Product Management

Tanner EDA front end: S-Edit integrates with Berkeley Fast Analog Simulator
W-Edit – is the waveform viewer

Who is Tanner – full suite for custom IC design
– 22 years in industry
– AMS focus
– First on Windows (also Linux)
– 20K licenses, 67 Countries

S-Edit – Schematics (Import Mentor and Cadence legacy data)
– Cross probe between schematics and layout
– Checking
– Launch simulation, make measurements

Berkeley Analog Fast Spice (AFS)
– About 5 to 10X faster than SPICE
– 10M element capacity

W-Edit – setup measurements
– Scripting for sophisticated measurements
– Built in measurement functions

Layout editor – L-Edit

SDL – schematic driven layout

HiPer DevGen – layout generators

HiPer Verify – Netlist extraction tool (Takes Calibre or Assura decks as inputs)

HiPer PX – parasitic extraction
Why choose Tanner?
– Economic price
– Installed base
– PDKs

Why not your own Fast SPICE?
Easier to partner with a leader already.

John Zuk

Last year – Hiper DevGen (Dublin based, IC Mask)
– This year added: Resistor arrays for matching, adding mosfet array generators, adding current mirrors
– Focus is on analog blocks

SDL – read in netlist analyze it, find current mirrors, use Hiper Devgen automatically

Interactive DRC – close enough to final rules, then HiPer Verfiy in batch to complete the layout verification

Open Access – in integration now, L-edit is first, S-edit is next. PC –based we donated technology that they didn’t even have.
– Took more effort than anticipated.
– Working with Si2 to define what OA should be
– iDRC and iLVS are in the future, after L-edit and S-edit, waiting to be embraced
– IPL Constraints – looking at that as well, designer notes, will be part of S-edit
– V16 is due in October and will be the first to support OA

iPDK – Looks more practical than Open PDK
– In V17 this would be supported in 2012, beta by June 2012

Resell BDA tool – 1st line of support,

OEM – parasitic extraction tool (Tuo Delft in Netherlands, HiPer PX extraction)
– Hiper devgen

Tanner version – scaled down version limited by processors and total elements, lighter version, token based
– Worldwide sales agreement
– First copy to be sold very soon

Fiscal Year – 140 new customers in 2011

Greg

3D field solver as an upgrade

V16 – multi user now available

OA – realtime collaboration on the same database

ClioSoft – what is the cost of this?

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Blue Pearl at DAC

Blue Pearl at DAC
by Daniel Payne on 06-14-2011 at 1:03 pm
Categories: Uncategorized

Intro
It’s all about analyzing RTL and creating timing constraints at Blue Pearl, so I stopped by their booth on Tuesday morning to get an update on what’s new for 2011.

Notes

What’s New in 2011 at Blue Pearl Software

New designer experience, ease of use. Brand new GUI.

Work with RTL to synthesis tools to get best timing in your layout.

GUI – windows 7 and Linux, same look and feel.
–All new in 2011
–Inline help

Blue Pearl Analyze – Linting, race checks,
–Demo: support languages: verilog 1995, 2001, 2005, System Verilog, VHDL 2008
–Read your libraries
–Modules can be grey box or black box
–Clocks can be automatically identified or manually setup
–Schematic view auto generated based on your source code
o Cross probe between RTL and schematic view
o Quick browsing of hierarchy
–About 250 checks are run on the source code
o LInting
o Low power
o Timing constraints
o DFT
o CDC
o Etc
–Visual Verification
o 200K gate design
o Lint, structural checking, CDC analysis, CDC identification,
o Using FlexLM for licensing
o False path, multicycle paths
o Only 45 seconds needed on a laptop
o Faster than others who synthesize to gates, instead of staying at RTL level
o About 10X faster than other approaches (Atrenta)
o Run the tool from the bottom up
o All the CDC unsynched paths are shown in text list, clicking creates a schematic view
o Designer decides what to do with the violations to accept or ignore
o User can filter the messages, warnings, errors (Use rules, patterns, modules, names, severity)

Blue Pearl Create –
–Creates an SDC file automatically
–All false paths are displayed in a tree view and schematic view
–Assertions are shown for each false path
–An audit trail explains why the control values are creating a conflict
–The SDC file will help other tools (STA, Synthesis, ATPG) to reduce their run times
–Can save weeks of time compared to manual SDC constraint generation
–200K design run in minutes
–Customers: Microsoft, KLA, Cypress Technologies

Usage: Block level designs, run on PC or Linux boxes

Users: IC (Constraint generation), FPGA (Help on large designs like Virtex with 10M gates, PC and Windows. Find Clock Gating opportunities), IP (want more tool flexibility)

Version 5.0 (Blue Pearl Software Suite)

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Synopsys, ARM, Samsung, GLOBALFOUNDRIES (Part 2 of 2)

Synopsys, ARM, Samsung, GLOBALFOUNDRIES (Part 2 of 2)
by Daniel Payne on 06-14-2011 at 12:43 pm
Categories: Uncategorized

Dipesh Patel, VP Engineering, ARM Physical IP

Consumer demand for smart devices, short life cycles (SmartPhone, Tablets, Internet screens)

Processor speeds: 1GHz to 1.5GHz
SOC Memory: 600MHz to 1.2 GHz
How power efficient?
How is the layout density?

Standard Cells: multi-channel, multi-vt (4) libraries

Memory Compilers: single port, multi port, ROM
7 families to choose from

28nm libraries nominal VDD of 1.0V

Processor Optimization Package (POP)
–Physical IP
–Reference flow, documentation, guidelines
–ARM certified benchmarking

Cortex A9 – 1.3GHz performance now

Silicon Validated – created Test Chips for GLOBALFOUNDRIES and Samsung at 32nm and 28nm nodes

Fab Synch – migrate any design from one fab to another one

Ready to Start – http://designstart.arm.com/

Andy Potemski – Director of Global Technical Services, Synopsys

Lynx Design System – About 2 years old, design system of silicon realization tools
–Off the shelf productivity
–A core flow for building an ARM Cortex A9
–Configure Flow with High Performance Libraries and IP
o Use DesignWare or 3[SUP]rd[/SUP] party IP
–Optimize the methodology for design specific needs
–Optimize the design floor plan in the context of the full chip
o Quad core A9 floor plan
o Explore and optimize
–Optimize performance and power
o Detailed routing
o Trend analysis of design metrics like power, area, speed
–Optimize the design flow turn around time
o Track execution of all tools
o Analyze the profile of each tool
o Identify tool bottlenecks

Q: The ARM brochure says up to 25% higher performance or 80% less power. Can I get both?
A: That’s very difficult. It’s really a tradeoff that you have to choose between.

Q: How will work on 28nm help 20nm, especially in light of litho effects?
A: We’re collaborating early in the development of 20nm to learn from our Common Platform partners. Double patterning is needed for 20nm. Expect to see a 50% improvement in density going from 28nm to 20nm node. Computational lithography required on 20nm. Another level of litho complexity make architectural exploration a challenge. Trying to minimize the number of double patterning layers required.

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Synopsys, ARM, Samsung, GLOBALFOUNDRIES (Part 1 of 2)

Synopsys, ARM, Samsung, GLOBALFOUNDRIES (Part 1 of 2)
by Daniel Payne on 06-14-2011 at 12:26 pm
Categories: Uncategorized

Intro
The 28nm nodes is ready with foundry silicon, IP and EDA tools. Tuesday morning at the DAC breakfast I learned more about the 28nm eco-system.

Notes
Why 32/28nm
–Lower power, high integration requirements, mobile applications

What is Ready?
–IP is qualified (ARM, Memories, Foundation IP, SNPS IP, PDKs)
–August 2010 SNPS and GLOBALFOUNDRIES at 28nm
–June 2011 SNPS and ARM at 28nm (A15 core)
–June 2010 Samsung at 32nm with SNPS tools
–Common Platform – Lynx tool flow is ready, January 2011
–June 2011 GLOBALFOUNDRIES ready at 28nm
–Samsung qualifies 28nm
–Samsung at 35 tape outs at 32nm to date

Anna Hunter, VP Samsung
Technology Roadmap
–32nm LP: ready, HKMG process
o SRAM at .149um*um, tiny size
o Good yield at 86%
o Matches SPICE results
–28nm LP: ready
o Same HKMG as 32nm node
o Works with ARM IP and SNPS tool flow
–28nm LPH: under development (low power, plus higher performance modules)
o Will be up to 50% faster (with more leakage, 2.3X)
o Same HKMG
o Added strain to silicon
o Shuttles starting now
–20nm LPM: in development, PDK evaluation now. Ready by end of 2012.

Lynx – flow of SNPS tools and IP management, used by Samsung internally too

ARM CPU – 45nm >1GHz on Cortex A9
–32/28nm >1.35GHz on Cortez A15
–28nm LPH, >2.0GHz Cortex A15

IP Portfolio – High Speed, Memory, Mixed Signal
–ARM, SNPS<

Going from 45nm to 32nm more than 50% improvement in SRAM bit cell size

Turn key solutions from Samsung
–Design, Fab, Wafer Sort, Assembly, Final Test
–Working on TSV technology for higher integration on packaging

MPW – Run every quarter for 32nm and 28nm
–Will start 20nm in September

Fab sites – Korea( 20nm), Texas (40K wafers per month)

Jim Ballingall, VP Marketing at GLOBALFOUNDRIES
–AMD lead product used HKMG technology, quad core CPU with GPU integrated, 500GFlops, for notebooks
–Llano powered laptops later in June

Super Low Power – 28nm SLP (doesn’t use stressing), about 2.3GHz

High Performance Plus – 28nm HPP (uses stressing), about 3.1GHz

Global Solutions – Design Solutions, Technology, Design Infrastructure<

IP – in place

Fabs – New York, Germany, Singapore

MPW – 4 shuttles in 2011

20nm – working with Common Platform partners, area scaling of 50% from 28nm

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A Birds-Eye Overview of DRC+

A Birds-Eye Overview of DRC+
by Daniel Nenni on 06-13-2011 at 10:57 pm
Categories: EDA, Foundries, GlobalFoundries

The GlobalFoundries DRC+ platform is one of the most innovative DFM technologies and was well represented at #48DAC. In case you missed it, here is a reprint of a DRC+ overview from GFI just prior to #48DAC:

DRC (Design Rule Constraints) are the fundamental principles in constraining VLSI (Very Large Scale Integration) circuit designs to standardized physical and electrical manufacturability criterion.

Today’s component miniaturization and density technologies require continual reassessment of best practice applications to keep design geometries aligned with realistic manufacturing capabilities. Two-dimensional DRC layout patterns may prove to be mathematically and layout rules compliant. But, when they are applied at the extremes of the manufacturing process tolerances, lithographic printability issues still arise. DRC+ is a new methodology that can be implemented in identifying the issues around complex process methods.

DRC+ pattern based rule deck provided by GLOBALFOUNDRIES is a cutting-edge application that can not only identify the 2D pattern anomalies early on; it can efficiently identify these anomalies during the all stages of the design flow. DRC+ functions in the same fashion as traditional design constrained applications. However, it adds the function of associating a 2D pattern with each constraint which acts as a filter to localize where the constraint is applied.

The result of this functionality is that the DRC tool, running a DRC+ rule deck, will enforce tighter constraints only where the anomalies occur. For this discussion tip-to-side patterns are the subject.

An example of this implementation is shown in Figure 1, which enforces a tighter min-space +20nm line-end space constraint where the U-shaped pattern is found. DRC+ operates strictly on design geometries without any intrinsic understanding of the underlying manufacturing technology process. Therefore, the effectiveness of DRC+ depends heavily on the quality of the rule deck.

A Brief Overview
Figure 2 is an example of how DRC+ applies a “preferred” rule constraint to tip-to-side geometry. Each DRC+ rule includes a specific tip-to-side pattern, and a preferred rule, which has a more stringent constraint to be applied in that pattern situation. This example uses tip-to-side patterns that vary due to the surrounding context. In this case, the standard DRC rule specifies a constraint of ≥ 60nm, while the DRC+ rule deck adds a more stringent constraint of ≥ 80nm. A patterns that does not pass the standard DRC rule, will have the DRC+ rule applied.

One way to create DRC+ rules is to identify hotspots using printability verification simulation. Once identified, a DRC+ rule is crafted to disallow the problematic pattern in design. The DRC+ methodology employs an algorithmic approach to creating rules. Rather than using a hotspot as a starting point, it approaches the hot spot from the perspective of design, design style, and design variability to establish at the outset which patterns should be considered for DRC+ rules1. The result of DRC+ analysis is hot patterns rather than hotspots. This provides effective screening while enabling much higher efficiency and throughput than litho simulation of an entire chip.

A Bit More Detail
DRC+ uses a series of steps to identify pattern configurations. The first step is to develop situation classes. These are determined by extracting patterns from representative designs (see Figure 3) and developing a histogram of the situation classes. These classes can then be evaluated based upon permutations and occurrences.

The next step is to determine which of these situation classes have lower than average printability. These are the classes that, based upon the required constraint to ensure printability, become candidates for DRC+ rules (In the above graphic, it happens to be the tip-to-side distance). Then, a metric called Design-Induced Edge Printing Variability (DIEPV) is used to determine the printability of each class. DEIPV essentially represents printing error over the process window for a given situation—the greater the magnitude of DIEPV, the more printing error is likely.

Now, one must determine which situation classes are candidates for DRC+ rules. In the above case, a simple threshold algorithm can be implemented comparing the DIEPV statistics of each situation class to the values of the overall layout. Once the algorithm has been applied the data can be displayed graphically for analysis (see Figure 4).

Tool Implementation
DRC+ is compatible with both traditional and cutting-edge generation of EDA (Electronic Design Automation) tools. For this article, we will use Calibre® as an example. Figure 5 shows the error makers, DRC+ rule in question and its context (i.e., its situation). The equation-based DRC capability of Calibre® also provides specific hints on how to fix the violation. Where the physical verification platform is integrated into the physical design environment, most of the repairs can be done automatically by the physical design tool itself, such as the router.

Conclusion
DRC+ is a new methodology that algorithmically characterizes design variation through pattern classification. A traditional design rule is used to identify all design structures that share a common configuration. Then the 2D geometric situations (pattern variations) around the configuration are extracted and classified. Since all such classes share a common configuration, each situation class represents design variations of the basic configuration.

DRC+ uses statistics derived from measurements of the situation classes as an alternative to simple CD (critical dimension) or EPE (edge placement error) thresholds used in classic printability verification. By identifying which situation classes have bad printability statistics, we can algorithmically find DRC+ rules.

The benefits of DRC+ are gaining tremendous industry momentum as the world’s leading EDA suppliers are already releasing development tools that support GLOBALFOUNDRIES DRC+ rule sets in 28nm.

Tools that provide fast pattern matching capabilities make implementation of DRC+ straightforward. For the user it is mainly a matter of updating the standard DRC rule deck with the expanded DRC+ pattern-based rule deck provided by GLOBALFOUNDRIES. Performance is on a par with traditional DRC runs.

The GFI Concurrent Newsletter is HERE. There is a video presentation of DRC+ HERE.

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CyberEDA adds a Transistor-Level Debugger

CyberEDA adds a Transistor-Level Debugger
by Daniel Payne on 06-13-2011 at 6:34 pm
Categories: Uncategorized

Intro
I met with CK Lee, founder of Cyber EDA at his booth on Monday evening in San Diego. Last year I learned about their new SPICE circuit simulator named PCSIM, this year the new product is called ADDS-Debugger.



Notes
2010 – Announced a debugger

2011 ADDS Debugger – trace at the transistor level your design
– Signal tracing
– Post-layout debug

o Tracing – which signal triggered that net that rose or fall?
o Trace back to a Primary input
o Cross-probe between auto-generated Schematic and the waveforms
o Pricing: $50K per year
– ADDS Wave
o Pricing: $2K per year
– PCSim
o Pricing: $25K per year
o Post-layout simulation speed improved, 3X
o True SPICE simulator, flattened
o Compete with HSPICE, SPectre, ELdo

Customers – Ali (Taiwan)
– Extreme DA

Based: Santa Clara, CA

Employees: 10

Next Year: Double revenues

Sales: Direct mostly, some distributors

Summary
ADDS Debugger reminded me a lot of what Concept Engineering has been offering for several years now in a transistor-level debugger. What makes this different is that you’re inside of a circuit simulation run when you can visualize the netlist as a schematic and see the node voltages and branch currents.

The SPICE circuit simulator market is crowded with many EDA vendors (Synopsys, Mentor, Cadence, Magma, Berkeley, Tanner EDA), so Cyber EDA has to do something special in order to make PCSIM stand out from the crowd (speed, accuracy, capacity, features).